Sort by
  1. Language:All
  2. Category:verilog
  3. Time:ALL
  4. View:500—1000 times
Remove all
Language More Hide
Category More Hide
Time
View
More

1024-bit RSA encryption algorithm

Description of the RSA algorithmSelect two large prime numbers with the same length, p and q , Calculate the product:n = pqThen pick a random encryption key, make e, (p-1) (q-1) are prime numbers from each other.Finally, calculate the decryption key d use Euclid extended algorithm to meet the requ...

Histogram equalization FPGA implementation

Real-time image histogram equalization in FPGA, effective use of FPGA chip-chip resources, no need to add external memory chips. The code is based on YCbCr, actually only the luminance histogram equalization, time after which a synchronous CB,CR color components, avoiding partial color problem! Code...

FFT FFT algorithm based on Verilog

This code implements 128 points, FFT calculation of 16-bit integers, Quartus II version 8.0, as verified by simulation, timing constraints and practical verification program features can fully meet demand under normal circumstances, clocking 150Mhz....

Implementation of Pipeline 2D-DCT for MPEG Compression

The 2-D DCT transforms a block of N x N pixels from the spatial domain into the frequency domain. Before compression, image data in memory is divided into several blocks. Each block consists of 8x8 pixels. Fig. 2 shows that in the resulting coefficient block, the coefficient in t...

Realization of image median filtering FPGA

The realization of image algorithm based on FPGA, including the verification of the algorithm of MATLAB is implemented in the FPGA algorithm, using Xilinxdevelopment environment, verified by....

Gigabit network programs available from Altera Corporation

The source code download Altera official website, providing 3C120 for use with Altera Corporation Board, but the program can still draw on Gigabit Ethernet. It uses the IP provided by Altera Triple-Speed-Ethernet nuclear Qsys-system is constructed, and then write programs in nios2....

ddr3 sdram controller

This is the verilog code for DDR3 SDRAM controller. Welcome to download and use. Thank you for your support!!!...

code verilog cordic core

A 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included manual for details...

Pipelined FFT/IFFT 64 points processor

64 -point radix-8 FFT.   Forward and inverse FFT.    Pipelined mode operation, each result is outputted in one clock cycle, the latent delay from input to output is equal to 163 clock cycles, simultaneous loading/downloading supported.   Input data, output data, and co...

SPI Verilog implementation of detailed and comprehensive

Verilog implementation of SPI (a very comprehensive and detailed, but also with a SPI algorithm annotations), this code is the SPI interface's Master and slaver Verilog source code...

prev 1 2 3 4 5 6 7 next

LOGIN

Don't have an account? Register now
Need any help?
Mail to: support@codeforge.com

切换到中文版?

CodeForge Chinese Version
CodeForge English Version

Where are you going?

^_^"Oops ...

Sorry!This guy is mysterious, its blog hasn't been opened, try another, please!
OK

Warm tip!

CodeForge to FavoriteFavorite by Ctrl+D