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Verilog HDL design and development laboratory

The most detailed collection of Verilog examples, rapid entry to the master. As an experimental tutorial this tutorial is divided into two parts: the FPGA hardware system based on Verilog and advanced interface design experiments. For the beginner can quickly get started. For those who have come int...

Complete SD controller! Supported file systems.

32-bit Wishbone Interface • DMA • Buffer Descriptor • Compliant with SD Host Controller Spec version 2.0 • Support SD 4-bit mode • Interrupt-on-completion of Data and Command transmission • Write/Read FIFO with variable size • Internal implementation of CRC16 for data lines and...

aynchronous fifo project

First-In First-Out (FIFO) memory structures are widely used to buffer the transfer of data between processing blocks. High performance and high complexity digital systems increasingly are required to transfer data between modules of differing and even unrelated clock frequencies. The dual-clock...

floating point adder

verilog code coded in xilinx used to add 2 floating point numbers.... and the technique used in this coding is piplining........

nand flash simulation model

NAND flash chip for IC chip design verification of simulation models; include model and test platform for NAND Flash controller design or verification personnel are very helpful! In addition, attach the Micron chip documentation, see PDF attachment...

USB Driver and VGA Interface for FPGA

This is source code for a USB bouncing ball and VGA driver kit for the Altera DE2-115 board. Note that it's in SystemVerilog which is 100% compatible with verilog (ie you can rename the files as .v and it still works). I'd suggest using a de2 board for compilation as that's what I'm using. a test im...

High efficiency LDPC code encoder FPGA development, VerilogHDL, and MATLAB simulation

Application backgroundWIMAX standard uses LDPC code as its optional channel encoding program. The WIMAX standard is the fourth global 3G standard for ITU, WCDMA, CDMA200, and TD-SCDMA in 2007. LDPC code with its excellent error correction performance has become a hot research topic in recent years....

Double precision floating point core Verilog

Application backgroundIEEE-754 compliant double-precision floating point unit. 4 operations (addition, subtraction, multiplication, division) are supported, as are the 4 rounding modes (nearest, 0, +inf, -inf). This unit also supports denormalized numbers, which is rare because most floating point u...

Asynchronous clock domain crossing fifo design

Asynchronous clock domain crossing design a FIFO fifo design is one of the most common problems encountered by ASIC designers. This article focuses on howSample design FIFO-- This is a deceptively simple but complex task. The outset, we should note, FIFO is typically used transition clock domai...

Floating Point Unit

This document describes the Verilog double precision floating point core, these cores are designed to meet the IEEE 754 standard for double precision floating point arithmetic. Floating Point IP Core (Verilog) The floating point IP core is separated into 7 source files: 1. fpu_double.v...

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