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network on chip

Design deals with minimizing the router port from five port to three port so that we can save power and area....

Cursor procedures _verilog

Move the cursor program for newcomers to learn for newcomers to enhance their ability to better, the couple quickly grasp the basic idea of writing programs....

FIR Filter Quartz Project

The Low power Finite Impulse Response (FIR) filter for the Digital signal processors (DSP) applications. Since it’s a datapath arithmetic architectural change, the proposed architecture can be applied to any hierarchical architecture where power is the major constraint. Designs were...

3d-dwt

The code is developed for 3d discrete wavelet transforms...

1 bit adpcm codec :: Overview

Audio Codec(ADPCM 1-Bit)  The code is ready for Altera Cyclone-II DE1 Starter board and it is tested, you can modify codes and use them in any project.  Core Description:  Sampling Frequency: 44100Hz  Channels: Stereo  Bit-rate: 1 Bit Per Sample(So it is: 44.1 * 2 = 8...

uart

In FPGA using Verilog implementation of the UART serial communication module, contains divider module, receiving module, sending module can change the baud rate, suitable for beginners to learn has on the board has been verified....

SSRAM(3_I/O)_Update

Updtae my code : http://www.codeforge.com/article/311141 This code modify: Altera)......

CPU32_adder

introduce the verilog language and use this to implement the calculation two 32-bit numbers including the multiplication.  In the codes, I input my CWID and 41411 to validate the function. you can change the HEX files to calculate different value. Architecture: Carry-Ripple+Carry-Skip....

CPU32_adder

introduce the verilog language and use this to implement the calculation two 32-bit numbers including the multiplication.  In the codes, I input my CWID and 41411 to validate the function. you can change the HEX files to calculate different value. Architecture: Carry-Ripple+Carry-Skip....

Verilog LDPC码

module LDPC (clk,reset,             data_in, data_in_en,             velocity, /*输入信号码率选择*/             data_out, data_out_en,             indic...

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