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Verilog LDPC码

module LDPC (clk,reset,             data_in, data_in_en,             velocity, /*输入信号码率选择*/             data_out, data_out_en,             indic...

Multiple levels of China

Application background4 way associative multilevel cahe using verilog. Can be ran in Xilinx software- ISIM simulator.4 way associative multilevel cahe using verilog. Can be ran in Xilinx software- ISIM simulator.4 way associative multilevel cahe using verilog. Can be ran in Xilinx software- ISIM sim...

robot line tracking

This is an assembly code in picoblaze for a line tracking bot....

upp 接口,verilog

FPGA之间通信,或者FPGA和DSP之间通信的接口协议,用verilog代码编写,验证可用!...

基于FPGA的16QAM的设计

设计了基于FPGA的16QAM的设计方法。包括调制和解调。...

32 bit carry look ahead adder

Carry lookahead depends on two things:Calculating, for each digit position, whether that position is going to propagate a carry if one comes in from the right.Combining these calculated values to be able to deduce quickly whether, for each group of digits, that group is going to propagate a carry th...

7位数码管的显示

实现7位数码管的显示,可以优先解决用户很多问题,不懂得可以问我,不用客气,7位数码管的显示很简单的...

国密SM4 verilog实现

国密SM4 verilog 实现 本算法是一个分组算法。该算法的分组长度为128比特,密钥长度为128比特。加密算法与密钥扩展算法都采用32轮非线性迭代结构。...

verilog实现千兆以太网UDP传输

verilog实现千兆以太网udp传输,具有发送和接收功能。同时有CRC校核代码。学习FPGA的很好的参考资料,值得大家下载。...

verilog实现VGA显示

verilog实现VGA显示。有源代码,大家可以下载学习。...


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