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Radix-2 FFT processor using Radix-2 Cordic Algorithm

This is the working Verilog code of Radix-2 FFT processor using Radix-2 Cordic Algorithm...

数字代码管显示0-9

开发板管脚有利于显示从0-9的所有数字,能够依次显示,能自己设定时间。字体会变化。...

elevator双电梯实现

功能描述:,设计一个 6 层楼(1~6)全自动双电梯控制电路,其功能如下:(未考虑到的细节可参照天河楼电梯运行规律) ◆每层楼电梯入口处设有上,下请求开关各1,电梯内设有乘客到达层次的停站请求按键。(一楼没有...

802.11a的基带检测

802.11a的基带分组检测的verilog实现,其使用了分组检测的优化算法——延时相关保存算法,具有由于的检测性能。...

The use of ip core

简单介绍一下FPGA中锁相环的IP使用,因为我们在编程的过程,会用到很多时钟,简单分享一下,PLL IP的使用...

N-clock Divider

Verilog Code for N-Clock Divider. An N-Clock divider is used to synchronize the frequencies for different machines....

verilog

lbus总线:一般是两个FPGA之间的相连接总线。或者其余器件与FPGA之间的数据总线。一般的时候会设计到双向数据总线。如何完成读写的控制?这里介绍一种简易稳定的处理方法。利用IOBUF完成双向总线。...

NAND FLASH控制器

NAND FLASH的控制器,Micro的样例,MCU端口有用到wishbone总线(软硬Core均可以)...

FPGA SDRAM读写

SDRAM即同步动态随机存储器,同步是指memory工作需要同步时钟,内部命令的发送与数据的传输都以它为基准;动态是指存储阵列需要不断地刷新来保证数据不丢失;随机是指数据不是线性依次存储,而是自由指定地址进行数据读...

fft_fpga_dit

Decimation-In-Time Fast Fourier Transform I've tried to make the implementation simple and well documented. I have not tried to make it efficient. dit.v - Contains main module. buffer.v - Contains a module for a single butterfly step. generate_twiddlefactors.py - Contains function to gene...


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