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CNN的Verilog实现

This project is a FPGA based implementation of first Convolutional Layer of AlexNet. The accelerator is developed using Verilog....

CPU of LC3-b

this sourse code is all design of a CPU 16 bit ,core LC3-b. It consists of small modules and a top module that connects small modules into a complete block. There is also a testbench file to check if the design is running correctly or not...


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