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CNN的Verilog实现

This project is a FPGA based implementation of first Convolutional Layer of AlexNet. The accelerator is developed using Verilog....

vivado2017+下的HDMI环路视频代码(AX7103)

在黑金AX7103板子上(A7)实现的demo工程中,存在一些bug。给与修正...

16-bit vedic multiplier

8X8 multipliers to develop 16X16 multipliers. Here we need to first design 16bit and 24 bit adders and by proper instantiating of the module and connections  we have designed a 16X16 bit multiplier. ...

CONNECT Network Verilog

/* ========================================================================= *  * CONNECT - CONfigurable NEtwork Creation Tool * Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University *  * ==========================================================...

CPU of LC3-b

this sourse code is all design of a CPU 16 bit ,core LC3-b. It consists of small modules and a top module that connects small modules into a complete block. There is also a testbench file to check if the design is running correctly or not...

FPGA驱动DM9000

通过FPGA驱动DM9000的程序源代码,可以实现UDP协议传输,长时间测试速率不掉,可以参考...

NAND FLASH控制器

NAND FLASH的控制器,Micro的样例,MCU端口有用到wishbone总线(软硬Core均可以)...

匹配滤波器的verilog实现

运用quatusii工具基于verilog实现匹配滤波器...

基于OFDM的通信系统系带设计

基于XILINX FPGA的OFDM通带系统设计,包括书和代码...

一个verilog的MP3解码项目

//***********************************************************//data        : 2007-07-11 11:30:00 //version     : 1.0////module name : Mp3Decode////modification history//---------------------------------//firt finish  2006//        &nbs...


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