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▍Arm frid_verilog core code

Application background// Address Register //   Jeffrey J. Cook (jjcook) `define AR_ALU_SEL 2'b00 `define AR_PC_SEL 2'b01 `define AR_PC_4_SEL 2'b10 `timescale 1ns/100ps module addr_reg(AR_Bus_Alu, AR_Bus_PC, AR_Bus_PC_4, AR_Bus_Sel, AR_Output_Bus, sysclk); input [31:0] AR_Bus_...