▍VGA display snake
Application backgroundMicrocomputer principle of comprehensive experiment, VGA display Snake game, based on the development of NEXYS4....
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▍H264 IP core written in Verilog
size:12.0pt;font-family:"">H.264/AVC 基线解码器 IP 核心。 可以在目录下找到用法说明： trunk/doc/nova_spec.doc 此外包含矢量文件。 Extremmely 容易理解。...
▍Verilog examples
size:14px;">学习verilog中常见的编程方法和例子。欢迎大家下载、试用。谢谢大家的支持！...
▍reconfigurable fir filter vhdl code
this is an fir filter implementation code for a reconfigurable fir filter design coded in vhdl language...
▍Motor SVPWM speed control VHDL source code
This is a motor SVPWM Speed control VHDL source code control procedures, including the main program and test rtl simulation program sim...
▍VHDL for 16 bit Time Domain Convolution
Convolution is a common operation in digital signal processing. In this project, I created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism to improve performance compared to a microprocessor. Convolution takes as input a signal and a kernell The...
▍turbo coder
日志-BCJRARCHITECTUREConventionalLUT-日志-BCJR 体系结构的能量消耗不通过简单 reducingtheir 时钟频率和吞吐量大大减少。这促使我们新型建筑便开始步入 ACS 基础电路系统是专门为了在具有最少的硬件复杂度，因此较低的能耗。< 跨度 s...
▍Verilog Code for 8 bit array multiplier
size:14px;">我写的 verilog 8 位阵列乘法器。接受两个 8 位数字，并给出 16 位的结果。...
▍8 bit CPU design
height:1.5;">组成CPU的基本部件有运算部件、寄存器组、微命令产生部件和时序系统等。这些部件通过CPU内部的总线连接起来，实现他们之间的信息交换。其中运算部件和一部分寄存器属于运算器部分；另一部分寄存器属于、微命...
▍用FPGA verilog hdl实现千兆以太网MAC。
Using FPGA verilog hdl realize Gigabit Ethernet MAC....
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