▍H264 IP core written in Verilog
A well-written H.264/AVC Baseline Decoder IP core. Usage instructions can be found under directory : trunk/doc/nova_spec.doc Also contains testbench file. Extremmely easy to understand....
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▍reconfigurable fir filter vhdl code
this is an fir filter implementation code for a reconfigurable fir filter design coded in vhdl language...
▍Motor SVPWM speed control VHDL source code
This is a motor SVPWM Speed control VHDL source code control procedures, including the main program and test rtl simulation program sim...
▍VHDL for 16 bit Time Domain Convolution
Convolution is a common operation in digital signal processing. In this project, I created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism to improve performance compared to a microprocessor. Convolution takes as input a signal and a kernell The...
▍Verilog Code for 8 bit array multiplier
I have written verilog for 8 bit array multiplier . Accepts two 8 bit numbers and gives 16 bit result....
▍Verilog examples
Learn verilog Common programming methods and examples. Welcome to download and trial. Thank you all for your support!...
▍turbo coder
CHAPTER2LUT-LOG-BCJRARCHITECTUREThe energy consumption of conventionalLUT-Log-BCJR architectures cannot be significantly reduced by simply reducingtheir clock frequency and throughput. This motivates our novel architecture ofimplementing the basis ACS circuit in the system which is specifically desi...
▍用于FPGA的huffman算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。...
The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms....
▍用FPGA verilog hdl实现千兆以太网MAC。
Using FPGA verilog hdl realize Gigabit Ethernet MAC....
▍3x3 median filter FPGA implementation (VERILOG)
3x3 median filter FPGA implementation (VERILOG)...
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