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H264 IP core written in Verilog

A well-written H.264/AVC Baseline Decoder IP core. Usage instructions can be found under directory : trunk/doc/nova_spec.doc Also contains testbench file. Extremmely easy to understand....

reconfigurable fir filter vhdl code

this is an fir filter implementation code for a reconfigurable fir filter design coded in vhdl language...

Verilog Code for 8 bit array multiplier

I have written verilog for 8 bit array multiplier . Accepts two 8 bit numbers and gives 16 bit result....

Motor SVPWM speed control VHDL source code

This is a motor SVPWM Speed control VHDL source code control procedures, including the main program and test rtl simulation program sim...

turbo coder

CHAPTER2LUT-LOG-BCJRARCHITECTUREThe energy consumption of conventionalLUT-Log-BCJR architectures cannot be significantly reduced by simply reducingtheir clock frequency and throughput. This motivates our novel architecture ofimplementing the basis ACS circuit in the system which is specifically desi...

用于FPGA的huffman算法的HDL编码,包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。...

The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms....

16/64 point FFT

This is a FFT library function by using VHDL code. It can switch the length of FFT between 16 point and 64 point. It contains the butterfly, twiddle factor, ROM, RAM and so on. And it can successfully run on Quartus 2 or other software....

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