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H264 IP core written in Verilog

A well-written H.264/AVC Baseline Decoder IP core. Usage instructions can be found under directory : trunk/doc/nova_spec.doc Also contains testbench file. Extremmely easy to understand....

Verilog Code for 8 bit array multiplier

I have written verilog for 8 bit array multiplier . Accepts two 8 bit numbers and gives 16 bit result....

reconfigurable fir filter vhdl code

this is an fir filter implementation code for a reconfigurable fir filter design coded in vhdl language...

Motor SVPWM speed control VHDL source code

This is a motor SVPWM Speed control VHDL source code control procedures, including the main program and test rtl simulation program sim...


The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms....

16/64 point FFT

This is a FFT library function by using VHDL code. It can switch the length of FFT between 16 point and 64 point. It contains the butterfly, twiddle factor, ROM, RAM and so on. And it can successfully run on Quartus 2 or other software....

VHDL for 16 bit Time Domain Convolution

Convolution is a common operation in digital signal processing. In this project, I created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism to improve performance compared to a microprocessor. Convolution takes as input a signal and a kernell The...

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