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H264 IP core written in Verilog

A well-written H.264/AVC Baseline Decoder IP core. Usage instructions can be found under directory : trunk/doc/nova_spec.doc Also contains testbench file. Extremmely easy to understand....

Verilog Code for 8 bit array multiplier

I have written verilog for 8 bit array multiplier . Accepts two 8 bit numbers and gives 16 bit result....

Verilog examples

Learn verilog Common programming methods and examples. Welcome to download and trial. Thank you all for your support!...

VHDL for 16 bit Time Domain Convolution

Convolution is a common operation in digital signal processing. In this project, I created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism to improve performance compared to a microprocessor. Convolution takes as input a signal and a kernell The...

VGA display snake

Application backgroundMicrocomputer principle of comprehensive experiment, VGA display Snake game, based on the development of NEXYS4....

VHDL 100 examples

Share online for some 100 examples suitable for FPGA learning for beginners. Inside there are some classic tricks....

VHDL realization of 3*3 matrix multiplication

Matrix multiplication vhdl implementation, dimension fixed, very instructive.Focus on understanding the interface, timing settings, delay control. Because the structure is relatively clear, not added stimulus file, you can write your own....

Waveform generator and sine waveforms generator based on VHDL language

Waveform generator and sine waveforms generator based on VHDL language, a total of two files, communication development platform. This is a typical black wave generator program and an arbitrary waveform generator program, members can refer to the study, introduction to VHDL is also helpful to-This i...


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