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turbo coder

日志-BCJRARCHITECTUREConventionalLUT-日志-BCJR 体系结构的能量消耗不通过简单 reducingtheir 时钟频率和吞吐量大大减少。这促使我们新型建筑便开始步入 ACS 基础电路系统是专门为了在具有最少的硬件复杂度,因此较低的能耗。< 跨度 s...

h264 encoder

size:16px;">h264 encoderthis 编码器参考与开 的基准配置文件— — frame.640X480 图片支持测试操作时钟与 Xilinx 达 100 兆赫。...

altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序,已经过matlab 和modelsim 验证,文件中包含TEST...

based search procedures and zigzag scanning procedures, and ModelSim matlab has been verified, the document contains TESTBENCH, directly available...

A complete description of PIC16 series of microcontrollers verilog

A complete description of PIC16 series of microcontrollers verilog...

Realization virtual electric piano based on VHDL

left:21.0pt;text-indent:12.0pt;"> This program design using VHDL language virtual keyboard. Hammond organ design consists of four modules: play module keyplay, auto play module AutoPlay, check gauges and display module table and frequency module fenpin. Plays modules keyplay under the key key in...

Implement VHDL-based AES encryption algorithm

family:arial, 宋体, sans-serif;font-size:14px;line-height:24px;text-indent:28px;white-space:normal;background-color:#FFFFFF;">高级加密标准(英语:Advanced Encryption Standard,缩写:AES),在密码学中又称Rijndael加密法,是美国联邦政府采用的一种区块加密标...

Ago in the school curriculum design, the use of Verilog CPU prepare a procedure

Ago in the school curriculum design, the use of Verilog CPU prepare a procedure under the board...

CCSDS predictive coding

The latest FPGA implementation of CCSDS standard hyperspectral image compression algorithm, using VHDL implementation. Please refer to. Definitely good value for money, I hope to help you design!...

binoc router architecture for high throughput on chip communication

align:center;"> 噪音容忍和更快的芯片通信使用 BINOC 模型 摘要 网络芯片 (NoC) 已成为最有前途的和合理的解决方案,用于连接许多核心的系统芯片 (SoC)。在常规的 NoC 体系结构中邻近路由器通过硬有线单向沟通渠道相连...

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