Sort by
  1. Language:VHDL
  2. Category:All
  3. Time:ALL
  4. View:300—500 times
Remove all
Language More Hide
Category More Hide
Time
View
More

Realization virtual electric piano based on VHDL

This program design using VHDL language virtual keyboard. Hammond organ design consists of four modules: play module keyplay, auto play module AutoPlay, check gauges and display module table and frequency module fenpin. Plays modules keyplay under the key key indicates the pitch index_key; auto...

Implement VHDL-based AES encryption algorithm

Advanced Encryption Standard (English: Advanced Encryption Standard, abbreviation: AES), also known as Rijndael encryption method in cryptography, a block encryption standard adopted by the US federal government. This standard is used to replace the original DES, has been widely analyzed and multi-...

FPGA source audio signal Analyzer

Audio signal through consists of the OPAMP and the resistance of the 50Ohm impedance matching circuit to meet the input impedance 50 Ohm system requirements, calculation of signal power. In order to ensure that this signal is undistorted sampled signals through the cut-off frequency for the 10Khz an...

VHDL-based design and analysis of digital clock

Digital Clock is a digital circuit implementation, minutes, seconds, timing devices, compared with the mechanical clock has a higher accuracy and intuitive, and no mechanical devices, with longer life, so it has been widely use. In principle figure is a typical digital circuit, including combination...

FPGA implementation of cordic

CORDIC (Coordinate Rotation Digital Computer) algorithm for coordinate rotation digital calculation method is J.D.Volder1 first proposed in 1959, mainly used for trigonometric, hyperbolic, exponential, logarithmic calculation. Which basic plus and shift operation instead of multiplication, making th...

Using Verilog languages realize NAND Flash block to control access as well as th

Using Verilog languages realize NAND Flash block to control access as well as the synchronization FIFO control...

FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输,已验证,直接可用...

FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available...

prev 1 2 3 4 5 6 7 8 9 10 ... 15 next

LOGIN

Don't have an account? Register now
Need any help?
Mail to: support@codeforge.com

切换到中文版?

CodeForge Chinese Version
CodeForge English Version

Where are you going?

^_^"Oops ...

Sorry!This guy is mysterious, its blog hasn't been opened, try another, please!
OK

Warm tip!

CodeForge to FavoriteFavorite by Ctrl+D