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▍altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim 验证，文件中包含TEST...

altera fpga verilog design table DCT-based search procedures and zigzag scanning procedures, and ModelSim matlab has been verified, the document contains TESTBENCH, directly available...

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458

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a year ago

by op123

VHDL-FPGA-Verilog VHDL

▍A complete description of PIC16 series of microcontrollers verilog

A complete description of PIC16 series of microcontrollers verilog...

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441

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a year ago

by 91qq

VHDL-FPGA-Verilog VHDL

▍Implement VHDL-based AES encryption algorithm

Advanced Encryption Standard (English: Advanced Encryption Standard, abbreviation: AES), also known as Rijndael encryption method in cryptography, a block encryption standard adopted by the US federal government. This standard is used to replace the original DES, has been widely analyzed and multi-...

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431

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a year ago

by audrey

Embeded VHDL

▍8路视频光端机接收侧 VHDL源码，使用了千兆以太网SERDES芯片，基于TBI接口的PCM视频传输。...

8-Channel Video Optical Receiver side of VHDL source code, using the Gigabit Ethernet SERDES chip, based on the TBI interface PCM video transmission....

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304

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a year ago

by zhangjing

VHDL-FPGA-Verilog VHDL

▍This is a JPEG codec the VHDL code

This is a JPEG codec the VHDL code...

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336

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a year ago

by bob1

VHDL-FPGA-Verilog VHDL

▍FPGA source audio signal Analyzer

Audio signal through consists of the OPAMP and the resistance of the 50Ohm impedance matching circuit to meet the input impedance 50 Ohm system requirements, calculation of signal power. In order to ensure that this signal is undistorted sampled signals through the cut-off frequency for the 10Khz an...

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470

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a year ago

by 艾甜甜00

vhdl VHDL

▍VHDL-based design and analysis of digital clock

Digital Clock is a digital circuit implementation, minutes, seconds, timing devices, compared with the mechanical clock has a higher accuracy and intuitive, and no mechanical devices, with longer life, so it has been widely use. In principle figure is a typical digital circuit, including combination...

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475

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a year ago

by szy2008

vhdl VHDL