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altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序,已经过matlab 和modelsim 验证,文件中包含TEST...

altera fpga verilog design table DCT-based search procedures and zigzag scanning procedures, and ModelSim matlab has been verified, the document contains TESTBENCH, directly available...

FPGA source audio signal Analyzer

Audio signal through consists of the OPAMP and the resistance of the 50Ohm impedance matching circuit to meet the input impedance 50 Ohm system requirements, calculation of signal power. In order to ensure that this signal is undistorted sampled signals through the cut-off frequency for the 10Khz an...

Implement VHDL-based AES encryption algorithm

Advanced Encryption Standard (English: Advanced Encryption Standard, abbreviation: AES), also known as Rijndael encryption method in cryptography, a block encryption standard adopted by the US federal government. This standard is used to replace the original DES, has been widely analyzed and multi-...

8路视频光端机 接收侧 VHDL源码,使用了千兆以太网SERDES芯片,基于TBI接口的PCM视频传输。...

8-Channel Video Optical Receiver side of VHDL source code, using the Gigabit Ethernet SERDES chip, based on the TBI interface PCM video transmission....

FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输,已验证,直接可用...

FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available...

There is a PCI from PCI proprietors, PCI TARGET is open source, is the project d...

There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in t...

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