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H264 IP core written in Verilog

size:12.0pt;font-family:"">H.264/AVC 基线解码器 IP 核心。 可以在目录下找到用法说明: trunk/doc/nova_spec.doc 此外包含矢量文件。 Extremmely 容易理解。...

Verilog examples

size:14px;">学习verilog中常见的编程方法和例子。欢迎大家下载、试用。谢谢大家的支持!...

Verilog Code for 8 bit array multiplier

size:14px;">我写的 verilog 8 位阵列乘法器。接受两个 8 位数字,并给出 16 位的结果。...

Verilog code and simulation of Adaptive FIR filter waveforms

Adaptive filter means using the results of the previous time, the current time automatically adjust filter parameters, and the noise signal to accommodate changes in the characteristics of unknown or random, to obtain valid output, the design on the basis of MATLAB simulation using verilog achieve,...

FPGA VGA display experiments

This is an original VGA interface generation code. Is allowed to experiment in a certain size of image displayed on the computer monitor. Full realization of FPGA and PC monitors of the same letter. Code design is original....

Ov5620 used in FPGA

space:nowrap;font-size:14px;">ov5620在FPGA中的使用,本程序实现的功能是驱动摄像头OV5620,并将数据通过VGA接口输出,外接显示器即 看到摄像头的图像。...

SRAM full--Verilog language

This code is based on Xilinx FPGA development platform, using Verilog language, full SRAM all functions. Has been tested to verify....

FFT programs, based on Verilog

family:Simsun;line-height:16px;white-space:normal;background-color:#FFFFFF;">基于VHDL语言编写的FFT程序,256点,旋转因子存在自己编写的ROM里面,乘法器和数据存储采用的是IP核,若是需要使用,需要添加IP核,否则无法运行...

FPGA digital clock display

00-00,-can be changed in the middle of it. Using a nested loop structure...

4-bit counters Verilog code

One of the basics of Verilog source code, binary counters for a 4. Both counts can be achieved to realize the frequency of the clock signal, so that is one very practical introduction to Verilog code. On the basis of this code, you can make a variety of changes, to achieve different functionality....


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