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traffic light controler

indent:24.0pt;"> 交通灯控制芯片,该芯片具有如下功能:    (1)芯片采用SMIC 0.18工艺设计,外部采用5V电源供电,内部添加LDO模块使内部数字电路采用1.8V 的VDD、模拟电路采用3.3V VCC。    (2)芯片控制两...

1K SRAM seperate read and write ports, verilog code for ASIC design

1K SRAM, arranged as words of 32 bit, seperate read and write ports, verilog code for ASIC designusing even parity on count of 1's.also comes with testbench...

SOPC technology using Verilog create Hello program

SOPC technology FPGA Verilog hardware description language, writing in niosII  program    using Altera chip...

SRAM read/write

SRAM read/write operations using FPGA control, clear description of SRAM timing, how it works. Read or write operation is relatively simple, must be combined with the chip timing to write...

Dm900a module based on FPGA

indent:2em;color:#333333;font-family:Simsun;line-height:21px;white-space:normal;background-color:#FFFFFF;">DM9000A简介     主要特点     DM9000A实现以太网媒体介质访问层(MAC)和物理层(PHY)的功能,包括MAC数据帧的组装/拆分与收发...

FPGA accumulator

size:14px;">该项目是在的Quartus2实施,Altera公司的在DE2开发板....  设计有一个功能来积累给定的输出...这必须学习在Verilog HDL语言的基本编码..  这仍是如此基本的编程,它必须加强和改进..  使它成为一个更复杂的UT还...

8 bit up/down counter

7 board. It contains a slow clock in order to be able to see the transitions of counting either up or down. Test bench included...

Random number generation, Verilog code and documentation

size:16px;"> 有说明文档和代码,基于LFSR和CASR产生,一个由简单components43位LFSR的37位CaSR振荡器的频率的硬件随机数发生器随电压和温度状态寄存器不在上电复位。...


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