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IIC interface program

IIC interface program, master-slave control, switchable, VHDL code, the code defines clear, easy to use, just need an example of a top-level module, you have completed the hardware integration code, hoped has the help to do hardware friends...

Based on retrospective XilinxFPGA high

Based on retrospective XilinxFPGA high-speed Viterbi decoder...

高速Viterbi处理器的并行算法和结构

High-speed Viterbi processor parallel algorithm and structure...

用VERILOG语言实现16QAM的数字调制的程序,已经在ISE10.1版本中调试通过...

Using Verilog language realize 16QAM digital modulation procedures are in the debug version ISE10.1 through...

Programming category of communication a good serial communication implementation...

Programming category of communication a good serial communication implementation of the FPGA implementation of serial communication...

该脉冲位置调制与解调是通过脉冲的位置来反映调制信号的信息的...

The pulse position modulation and demodulation through the pulse position modulated signal to reflect the information...

FPGA

FPGA-based parallel architecture to achieve the full FFT design methodology, the use of the entire parallel increase in water structure, in a beat the clock to complete 32-point FFT computation function, the design maximum speed of up to 11ns...

From the " Wireless FPGA Design" a book excerpt down the WCDMA system c...

From the " Wireless FPGA Design" a book excerpt down the WCDMA system cell search FPGA to achieve the third part of the code....

此代码是用于DVB系统的信道编码模块,采用(204,188)编码方式,编码后前188个字节是信息位,后16个字节为冗余位。思绪仿真后,通过验证。...

This code is used for DVB systems channel coding module (204,188) encoding, after encoding the previous 188 bytes of information, and after the 16-bit byte for redundancy. Simulation thoughts through authentication....


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