▍Universal Asynchronous Receiver
Universal Asynchronous Receiver...
More
▍Discrete Multi Tone (DMT) is the modulation scheme used for Asymmetric Digital S...
speed Digital Subscriber Line (VDSL) systems....
▍Language
Verilog. The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae....
▍I2C to 8
bit Parallel Bus Slave Design...
▍在Max+plusΠ环境下用VHDL语言编写实现基于CPLD的CMI编译码器设计...
In Max+ plusΠ environment using VHDL language CPLD-based design of CMI codecs...
▍本文是SIMens公司培训的技术资料，有很好的使用价值
This article is SIMens corporate training technical information, there is a good value...
▍这是一个十分经典的异步收发器的设计，将发送和接受分开，并带有校验位，同时附赠结构图和仿真结构...
This is a very classic asynchronous transceiver will be designed to send and receive separately, and with a parity bit, and comes with charts and simulation of the structure...
▍Procedures relating to the keyboard interface, I get and I hope that helps
Procedures relating to the keyboard interface, I get and I hope that helps...
▍用vhdl做得CPLD静态两位数码管扫描 显示“10”两位数码管公用段选...
CPLD with VHDL done two static scan digital tube displays...
© 2014 CodeForge Dev Team All rights reserved. 