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AXI slave verilog code

Wrote AXI slaver Verilog code, hope to give you some inspiration...

Verilog Jpeg Encoder

This core takes as an input the red, green, and blue pixel values, like from a tiff image file, and creates the JPEG bit stream necessary to build a jpeg image. The core was written in generic, regular Verilog code that can be targeted to any FPGA. The core does not rely on any proprietary IP cores,...

Booth multiplier in verilog

This file describes the code for booth multiplier in verilog. the source code is simulated and verified for better results...

DDR2 controller, Verilog source code

Using Verilog prepared of DDR2 controller, achieved has DDR2 of reads and writes function, in Xilinx vietex5 Shang to achieved, achieved has Imaging algorithm in the of data turn home,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,...

Flash controller verilog code

This is the verilog code of Samsung K9 series Flash controller, it is complied and verified on FPGA development board, the verification environment is quartusii and modelsim combined platform. You can find the datasheet of K9 flash on the internet. The size of the flash is 1024*32....

1024-bit RSA encryption algorithm

Description of the RSA algorithmSelect two large prime numbers with the same length, p and q , Calculate the product:n = pqThen pick a random encryption key, make e, (p-1) (q-1) are prime numbers from each other.Finally, calculate the decryption key d use Euclid extended algorithm to meet the requ...

Cache memory

This code is the code cache, using the least recently used algorithm. Roughly 1000-2000 lines of code, the program includes cache replacement algorithm implementations. Selection of image rules, as well as all of the simulations....

SPI flash model written by verilog

M25Pxx ST company SPI flash memory Verilog simulation model, the model correctly describes the behavior of SPI flash memory, including reading, writing and erase operations, can be used to hang outside of the SOC with SPI interface, verify that the SPI interface....

Verilog code for the GPS baseband processing

GPS software receiver baseband processing Verilog programs, by spread spectrum demodulation, intermediate frequency data synchronization process converts the raw navigation data...

Realization of image median filtering FPGA

The realization of image algorithm based on FPGA, including the verification of the algorithm of MATLAB is implemented in the FPGA algorithm, using Xilinxdevelopment environment, verified by....

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