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AXI slave verilog code

size:14px;">自己写的 AXI slaver  verilog code,希望带给大家一些启示...

Verilog Jpeg Encoder

contained. This core has been simulated on many raw images with different quantification and Huffman tables....

FFT FFT algorithm based on Verilog

size:16px;">该代码实现128点,16位整型的FFT计算,基于Quartus II 8.0版本,已经过仿真,时序约束和实际验证,程序功能完全能达到正常情况下的需求,时钟可达150Mhz。...

Histogram equalization FPGA implementation

size:16px;">在fpga上实时实现图像的直方图均衡化,有效利用fpga芯片的片内资源,不需要添加片外的存储芯片。本代码是基于ycbcr处理的,其实只对亮度分量进行直方图均衡化,之后同步cb,cr颜色分量,避免偏色问题!代码接口为y...

HDMI interface chip (ADV7513) drive, 1080p60,720p60 colour bar test!

size:16px;">本工程实现了hdmi芯片的配置和驱动测试,可以选择性配置为1080P60,720p60,ddrmode等模式,1080p60和720p60格式的视频图像现在是主流格式,而ddrmode可以大大节省fpga上宝贵的管脚资源,本工程可选择性配置为444或422色彩空间...

DDR2 controller, Verilog source code

Using Verilog prepared of DDR2 controller, achieved has DDR2 of reads and writes function, in Xilinx vietex5 Shang to achieved, achieved has Imaging algorithm in the of data turn home,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,...

The DMAC module in AMBA Bus based on SOC design

This design is based on the SOC system, using AMBA Bus DMA data transfer mode control module design of DMAC, a total of five modules, proven design timing constraints and other requirements...

Booth multiplier in verilog

size:14px;">This file describes the code for booth multiplier in verilog. the source code is simulated and verified for better results...

Flash controller verilog code

This is the verilog code of Samsung K9 series Flash controller, it is complied and verified on FPGA development board, the verification environment is quartusii and modelsim combined platform. You can find the datasheet of K9 flash on the internet. The size of the flash is 1024*32....

1024-bit RSA encryption algorithm

1) are prime numbers from each other.Finally, calculate the decryption key d use Euclid extended algorithm to meet the requirement ofed = 1(mod(p–1)(q–1 ))i.e.d = e–1 mod((p–1)( q – 1 ))e and n are public key,d is private key...

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