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DDR2 controller, Verilog source code

Using Verilog prepared of DDR2 controller, achieved has DDR2 of reads and writes function, in Xilinx vietex5 Shang to achieved, achieved has Imaging algorithm in the of data turn home,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,...

1024-bit RSA encryption algorithm

Description of the RSA algorithmSelect two large prime numbers with the same length, p and q , Calculate the product:n = pqThen pick a random encryption key, make e, (p-1) (q-1) are prime numbers from each other.Finally, calculate the decryption key d use Euclid extended algorithm to meet the requ...

Cache memory

This code is the code cache, using the least recently used algorithm. Roughly 1000-2000 lines of code, the program includes cache replacement algorithm implementations. Selection of image rules, as well as all of the simulations....

FFT FFT algorithm based on Verilog

This code implements 128 points, FFT calculation of 16-bit integers, Quartus II version 8.0, as verified by simulation, timing constraints and practical verification program features can fully meet demand under normal circumstances, clocking 150Mhz....

Ethernet ip core verilog realization

Ethernet (Ethernet) Verilog IP core written in verilogHDL language Ethernet soft core, and Ethernet which helps a lot for learning Verilog language....

Realization of image median filtering FPGA

The realization of image algorithm based on FPGA, including the verification of the algorithm of MATLAB is implemented in the FPGA algorithm, using Xilinxdevelopment environment, verified by....

Implementation of Pipeline 2D-DCT for MPEG Compression

The 2-D DCT transforms a block of N x N pixels from the spatial domain into the frequency domain. Before compression, image data in memory is divided into several blocks. Each block consists of 8x8 pixels. Fig. 2 shows that in the resulting coefficient block, the coefficient in t...

AD7606 multi-channel data acquisition

Application background  AD7606 is an integrated 8 channel synchronous sampling data acquisition system, chip integrated input amplifierDevice, over-voltage protection circuit, two - step simulation of anti aliasing filter, analog multiplexer, 200 16 kSPS ADC SAR and a digital filter, 2.5 V...

FPU Floating point unit verilog VHDL

FPU (Floating Point Unit) is very useful in the moden ASIC and SOC designs. This module has been verified by FPGA and EDA env. But if you want to use it in a real project, please verify it with some formal method. ...

ddr3 sdram controller

This is the verilog code for DDR3 SDRAM controller. Welcome to download and use. Thank you for your support!!!...

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