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The DMAC module in AMBA Bus based on SOC design

This design is based on the SOC system, using AMBA Bus DMA data transfer mode control module design of DMAC, a total of five modules, proven design timing constraints and other requirements...

Viterbi decoder 2-1-7

viterbi decoding algorithm is a decoding algorithm for convolutional codes. Advantages not say. Drawback is bound to increase with the complexity of the algorithm is to increase the length of the fast. N is the path length constraint 7:00 to compare 64 there, the path goes to 8:00 128. (2 << (...

FPGA Verilong Ethernet

Under the fpga, written entirely verilong Ethernet program that can be tcp / IP communications, please do not use in commercial applications, thanks...

High efficiency LDPC code encoder FPGA development, VerilogHDL, and MATLAB simulation

Application backgroundWIMAX standard uses LDPC code as its optional channel encoding program. The WIMAX standard is the fourth global 3G standard for ITU, WCDMA, CDMA200, and TD-SCDMA in 2007. LDPC code with its excellent error correction performance has become a hot research topic in recent years....

Verilog HDL design and development laboratory

The most detailed collection of Verilog examples, rapid entry to the master. As an experimental tutorial this tutorial is divided into two parts: the FPGA hardware system based on Verilog and advanced interface design experiments. For the beginner can quickly get started. For those who have come int...

Verilog code for RS encoding and decoding

里的所罗门RS编解码方案,建立工程后可直接编译调试,对于学习RS编码原理的人员可以作为一个例子学习,也可以应用于相应的系统中...

Complete SD controller! Supported file systems.

32-bit Wishbone Interface • DMA • Buffer Descriptor • Compliant with SD Host Controller Spec version 2.0 • Support SD 4-bit mode • Interrupt-on-completion of Data and Command transmission • Write/Read FIFO with variable size • Internal implementation of CRC16 for data lines and...

aynchronous fifo project

First-In First-Out (FIFO) memory structures are widely used to buffer the transfer of data between processing blocks. High performance and high complexity digital systems increasingly are required to transfer data between modules of differing and even unrelated clock frequencies. The dual-clock...

ADPLL behavior model

The attached files contain the behavior model of ADPLL. The 6 bits TDC is used. A fast clock is used to count the the timing difference between the input reference clock and feedback clock. The TDC resolution is higher if the fast clock is faster. The digital loop filter produces 1...

Viterbi Convolutional coding and decoding algorithm for FPGA realization of the project

Convolutional coding uses 2,1,2 non-systematic Convolutional codes, decoding algorithm using the Viterbi algorithm, absolute engineering validation systems; supports up to 50Mbit/s more throughput...

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