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1024-bit RSA encryption algorithm

Description of the RSA algorithmSelect two large prime numbers with the same length, p and q , Calculate the product:n = pqThen pick a random encryption key, make e, (p-1) (q-1) are prime numbers from each other.Finally, calculate the decryption key d use Euclid extended algorithm to meet the requ...

The DMAC module in AMBA Bus based on SOC design

This design is based on the SOC system, using AMBA Bus DMA data transfer mode control module design of DMAC, a total of five modules, proven design timing constraints and other requirements...

FPGA implementation of QPSK modulation and demodulation algorithm code

The algorithm for QPSK modulation and demodulation carrier using Costas-loop synchronization algorithm, algorithm for bit timing by Gardner...

Realization of image median filtering FPGA

The realization of image algorithm based on FPGA, including the verification of the algorithm of MATLAB is implemented in the FPGA algorithm, using Xilinxdevelopment environment, verified by....

Histogram equalization FPGA implementation

Real-time image histogram equalization in FPGA, effective use of FPGA chip-chip resources, no need to add external memory chips. The code is based on YCbCr, actually only the luminance histogram equalization, time after which a synchronous CB,CR color components, avoiding partial color problem! Code...

Implementation of Pipeline 2D-DCT for MPEG Compression

The 2-D DCT transforms a block of N x N pixels from the spatial domain into the frequency domain. Before compression, image data in memory is divided into several blocks. Each block consists of 8x8 pixels. Fig. 2 shows that in the resulting coefficient block, the coefficient in t...

FPGA Verilong Ethernet

Under the fpga, written entirely verilong Ethernet program that can be tcp / IP communications, please do not use in commercial applications, thanks...

Viterbi decoder 2-1-7

viterbi decoding algorithm is a decoding algorithm for convolutional codes. Advantages not say. Drawback is bound to increase with the complexity of the algorithm is to increase the length of the fast. N is the path length constraint 7:00 to compare 64 there, the path goes to 8:00 128. (2 << (...

Verilog HDL design and development laboratory

The most detailed collection of Verilog examples, rapid entry to the master. As an experimental tutorial this tutorial is divided into two parts: the FPGA hardware system based on Verilog and advanced interface design experiments. For the beginner can quickly get started. For those who have come int...

Gigabit network programs available from Altera Corporation

The source code download Altera official website, providing 3C120 for use with Altera Corporation Board, but the program can still draw on Gigabit Ethernet. It uses the IP provided by Altera Triple-Speed-Ethernet nuclear Qsys-system is constructed, and then write programs in nios2....

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