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1024-bit RSA encryption algorithm

Description of the RSA algorithmSelect two large prime numbers with the same length, p and q , Calculate the product:n = pqThen pick a random encryption key, make e, (p-1) (q-1) are prime numbers from each other.Finally, calculate the decryption key d use Euclid extended algorithm to meet the requ...

Histogram equalization FPGA implementation

Real-time image histogram equalization in FPGA, effective use of FPGA chip-chip resources, no need to add external memory chips. The code is based on YCbCr, actually only the luminance histogram equalization, time after which a synchronous CB,CR color components, avoiding partial color problem! Code...

FFT FFT algorithm based on Verilog

This code implements 128 points, FFT calculation of 16-bit integers, Quartus II version 8.0, as verified by simulation, timing constraints and practical verification program features can fully meet demand under normal circumstances, clocking 150Mhz....

AD7606 multi-channel data acquisition

Application background  AD7606 is an integrated 8 channel synchronous sampling data acquisition system, chip integrated input amplifierDevice, over-voltage protection circuit, two - step simulation of anti aliasing filter, analog multiplexer, 200 16 kSPS ADC SAR and a digital filter, 2.5 V...

FPGA implementation of QPSK modulation and demodulation algorithm code

The algorithm for QPSK modulation and demodulation carrier using Costas-loop synchronization algorithm, algorithm for bit timing by Gardner...

Implementation of Pipeline 2D-DCT for MPEG Compression

The 2-D DCT transforms a block of N x N pixels from the spatial domain into the frequency domain. Before compression, image data in memory is divided into several blocks. Each block consists of 8x8 pixels. Fig. 2 shows that in the resulting coefficient block, the coefficient in t...

Ethernet ip core verilog realization

Ethernet (Ethernet) Verilog IP core written in verilogHDL language Ethernet soft core, and Ethernet which helps a lot for learning Verilog language....

Realization of image median filtering FPGA

The realization of image algorithm based on FPGA, including the verification of the algorithm of MATLAB is implemented in the FPGA algorithm, using Xilinxdevelopment environment, verified by....

Gigabit network programs available from Altera Corporation

The source code download Altera official website, providing 3C120 for use with Altera Corporation Board, but the program can still draw on Gigabit Ethernet. It uses the IP provided by Altera Triple-Speed-Ethernet nuclear Qsys-system is constructed, and then write programs in nios2....

ddr3 sdram controller

This is the verilog code for DDR3 SDRAM controller. Welcome to download and use. Thank you for your support!!!...

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