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High efficiency LDPC code encoder FPGA development, VerilogHDL, and MATLAB simulation

SCDMA之后于2007年获ITU批准的第四个全球3G标准。WIMAX 标准的LDPC码以其优异的纠错性能成为近年来人们研究的热点。研究了LDPC码的基本编码算法:生成矩阵法、基于近似下三角的编码算法、RU算法、LU算法之后,深入研究了基于RU...

Verilog HDL design and development laboratory

The most detailed collection of Verilog examples, rapid entry to the master. As an experimental tutorial this tutorial is divided into two parts: the FPGA hardware system based on Verilog and advanced interface design experiments. For the beginner can quickly get started. For those who have come int...

Complete SD controller! Supported file systems.

bit Wishbone Interface • DMA • Buffer Descriptor • Compliant with SD Host Controller Spec version 2.0 • Support SD 4-bit mode • Interrupt-on-completion of Data and Command transmission • Write/Read FIFO with variable size • Internal implementation of CRC16 for data lines and CRC...

ADPLL Design and Implementation on FPGA

size:16px;">本文提出了基于 FPGA 用 Verilog 和其执行的锁相环设计。采用 Verilog HDL 设计了锁相环。针对采用赛灵思 ISE 12.1 模拟器用来模拟Verilog 代码。本文给出了锁相环的基本块的详细信息。在本文中,中详细描述了的锁相环实现...

FPGA implementation of 16QAM modulation and demodulation

size:16px;">该源代码是实现14路并行的16QAM的调制,以及解调,其中还包含测试文件,已经在altera FPGA上面实现了其正确性,可以直接拿来使用。...

Viterbi Convolutional coding and decoding algorithm for FPGA realization of the project

size:16px;">Convolutional coding uses 2,1,2 non-systematic Convolutional codes, decoding algorithm using the Viterbi algorithm, absolute engineering validation systems; supports up to 50Mbit/s more throughput...

floating point adder

verilog code coded in xilinx used to add 2 floating point numbers.... and the technique used in this coding is piplining........

DM9000A test, send and receive, achieving UDP

height:normal;white-space:normal;">通过在SOPC中定制软核,在Quartus II中建立硬件工程,然后在NIOS II中建立3个工程,分别实现DM9000A测试、DM9000A自收发和基于DM9000A的UDP协议的例子。3个例子所使用的DM9000A的驱动是一样的。软件平台...

FPGA DDS generators

size:16px;">以DE2为开发平台,采用Veriolg语言编程,实现了DDS信号输出,频率,步进,波形输出均可调,采用Modelsim以及FPGA内嵌逻辑分析仪验证设计的正确性,可以满足一定的工程需求。...

Double precision floating point core Verilog

754标准的双精度浮点单元。4操作(加法,减法,乘法,除法)的支持,以及4的舍入模式(最近,0,Inf,-Inf)。本机还支持非规格化数,这是罕见的因为大多数浮点单位对非规格化数为零。单位可以运行在185 MHz的时钟频率高达...

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