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The DMAC module in AMBA Bus based on SOC design

This design is based on the SOC system, using AMBA Bus DMA data transfer mode control module design of DMAC, a total of five modules, proven design timing constraints and other requirements...

FPGA Verilong Ethernet

Under the fpga, written entirely verilong Ethernet program that can be tcp / IP communications, please do not use in commercial applications, thanks...

Verilog HDL design and development laboratory

The most detailed collection of Verilog examples, rapid entry to the master. As an experimental tutorial this tutorial is divided into two parts: the FPGA hardware system based on Verilog and advanced interface design experiments. For the beginner can quickly get started. For those who have come int...

ADPLL behavior model

The attached files contain the behavior model of ADPLL. The 6 bits TDC is used. A fast clock is used to count the the timing difference between the input reference clock and feedback clock. The TDC resolution is higher if the fast clock is faster. The digital loop filter produces 1...

DM9000A test, send and receive, achieving UDP

Through custom soft core in SOPC, established in the Quartus II hardware engineering, and 3 works established in the NIOS II, respectively DM9000A test, send and receive DM9000A-DM9000A and UDP protocol examples. 3 example using DM9000A drives are the same.Software platform: Quartus II 9.0 + Nios II...

sobel edge detection

This VHDL/Verilog or C/C++ source code is intended as a design reference which illustrates how these types of functions can be implemented.  It is the user's responsibility to verify their design for consistency and functionality through the use of formal verification methods.&nb...

Viterbi decoder 2-1-7

viterbi decoding algorithm is a decoding algorithm for convolutional codes. Advantages not say. Drawback is bound to increase with the complexity of the algorithm is to increase the length of the fast. N is the path length constraint 7:00 to compare 64 there, the path goes to 8:00 128. (2 << (...

APB protocol

APB master and slave implemented in verilog. State machines of both master and slave is designed, APB mainly is used for low bandwidth peripherals. ...

FPGA DDS generators

DE2 development platform, uses the Veriolg language programming realized DDS signal output, frequency and step wave output with adjustable using Modelsim and FPGA embedded logic Analyzer verifies the correctness of design, can meet the needs of engineering....

Verilog code for RS encoding and decoding

里的所罗门RS编解码方案,建立工程后可直接编译调试,对于学习RS编码原理的人员可以作为一个例子学习,也可以应用于相应的系统中...

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