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DE2_70_D5M_LTM

DE2_70_D5M_LTM mainly in the DE2-70 development of a video capture and LTM displayed on the platform process, the platform can be used as image processing and graphics hardware, the system can be improved and extended, such as video surveillance systems...

FPGA median filter _ISE and MATLAB program

Application backgroundThe bud Natu plus noise through median filtering, processing the output pixel value matrix, stored in txt. Read the txt pixel value from MATLAB, reset matrix output processed Lei Natu (noise)Key TechnologyMedian filtering algorithm core is to take 9 values (file is 3*3 window)...

Simple 32bit RISC CPU core

I am INHA Univ student at South korea. This is project result of coumputer architecture.IT's CPU Core, 32bit RISC system. It can be opreated at 300 MIPS. 1cycle / 1instruction system.It propose Simple Harvard Architecture. and Do simple Arithmetic logic....

micro sd card interface(sdmode)

size:16px;">This code implements an SD card interface driver functions is realized in sdmode read and write rates of 50Mbps, you can also add additional commands to sketch rates of 100Mbps, and file systems can be realized in this interface easily on the basis, so as to achieve the required function...

IFFT xlinx ISE development

size:16px;">用verilog编程语言实现的ifft程序,用的器件是赛灵思的,开发环境是ise,采用流水线结构,值得下载借鉴,蝶形算法采用基2分解,可用于数字滤波,信号处理等领域,希望那个大家多多支持.........

Cheap FPGA analog oscilloscope display

size:16px;">用廉价 FPGA  实现 模拟示波器方式的显示,含 Quartus II 工程文件,原理图 PCB 图。...

FPGA logic Analyzer

size:16px;">quartus verilog 逻辑分析仪, 检测数字信号(与示波器检测模拟信号对应),vga显示输出。经过本人调试可用。...

Time measurement based on FPGA and AD a/d conversion

left:21.2500pt;text-indent:-21.2500pt;">其中,技术指标如下AD采样率:1GSPS ,AD分辨率:8bit/s ,测距范围:30km ,测距精度:0.5ns。  实现方法为:采用250MHz的时钟信号,经移相倍频获得1GHz采样频率。FPGA发出信号,之后再接收回波。采...

coventional dct using verilog

列。离散余弦变换是图像处理 trnasform 有权从空间域向频率域图像中非常重要的。程序注释将帮助您了解该过程。...

FPGA'for' cycle

Written in the Verilog language for circulation and used to verify whether in the FPGA can writing a for loop in c, it turned out although the emulation to get the right result, but in real engineering are not compile-time takes 24 hours to complete, so I chose another method to loop through, after...

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