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The DMAC module in AMBA Bus based on SOC design

This design is based on the SOC system, using AMBA Bus DMA data transfer mode control module design of DMAC, a total of five modules, proven design timing constraints and other requirements...

Verilog HDL design and development laboratory

The most detailed collection of Verilog examples, rapid entry to the master. As an experimental tutorial this tutorial is divided into two parts: the FPGA hardware system based on Verilog and advanced interface design experiments. For the beginner can quickly get started. For those who have come int...

Complete SD controller! Supported file systems.

32-bit Wishbone Interface • DMA • Buffer Descriptor • Compliant with SD Host Controller Spec version 2.0 • Support SD 4-bit mode • Interrupt-on-completion of Data and Command transmission • Write/Read FIFO with variable size • Internal implementation of CRC16 for data lines and...

floating point adder

verilog code coded in xilinx used to add 2 floating point numbers.... and the technique used in this coding is piplining........

Viterbi Convolutional coding and decoding algorithm for FPGA realization of the project

Convolutional coding uses 2,1,2 non-systematic Convolutional codes, decoding algorithm using the Viterbi algorithm, absolute engineering validation systems; supports up to 50Mbit/s more throughput...

DM9000A test, send and receive, achieving UDP

Through custom soft core in SOPC, established in the Quartus II hardware engineering, and 3 works established in the NIOS II, respectively DM9000A test, send and receive DM9000A-DM9000A and UDP protocol examples. 3 example using DM9000A drives are the same.Software platform: Quartus II 9.0 + Nios II...

转载,fpga读取ov7670数据并用vga显示

这是在网上搜到的,具体的代码我也没没怎么弄明白,还是下载后自己研究。主要功能是应用fpga,ov7670数字感光芯片还有VGA组成视频显示系统,实时显示ov7670采集到的图像。...

Viterbi decoder 2-1-7

viterbi decoding algorithm is a decoding algorithm for convolutional codes. Advantages not say. Drawback is bound to increase with the complexity of the algorithm is to increase the length of the fast. N is the path length constraint 7:00 to compare 64 there, the path goes to 8:00 128. (2 << (...

Verilog code for RS encoding and decoding

里的所罗门RS编解码方案,建立工程后可直接编译调试,对于学习RS编码原理的人员可以作为一个例子学习,也可以应用于相应的系统中...

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