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Serial spontaneous resumption procedures

Serial received a spontaneous test functions, development environments quartus12.1 Baud rate setting 9600bps, available for testing of the Development Board serial port functions....

Ethernet 1000

In PVI receives 16 bit parallel digital stream ( video) , followed by a clock signal (Ft = 29 MHz) , lowercase (LINE) and personnel (FRAME) sync .Record information in PVI should occur on the rising edge of the clock Ft.Horizontal sync pulse "covers" a useful video broadcast via Ethernet....

Chip Controller

Chip Controller consists of a Control unit, 16 bit ALU with Memory Unit which executes various arithmetic and logical operations.This is simulated by using verilog in XILINX ISE Simulator. A detailed document is given and code for design of chip controller is  included....

Simple routine de2 led

The purpose of this exercise is to learn how to connect a simple input and output devices to an FPGA chip, and use these devices to achieve an electrical circuit. Our switches SW17-0 DE2 development boards will be used as input, and 7-segment LED displays as output. When you toggle a switch (Switch...


given angle generator logic is used in produces angles to the 16 point FFT processor. These angles are useful in twiddle factor calculation. ...

adding two 8 bit numbers

simple code for adding two numbers. get two numbers and enable as input. And if enable is true, perform addition else output high impedance value....

Hamming code

hamming encoder for 16bit is written in verilog language, which will run successfully in Xlinx tool and gives result.Basically hamming encoder is used in communication filed , which encrypts the data and transmits to the receiver which helps in data security. ...

Divider design

Signed a 5-bit integer divider design and production design requirements:Design a divides two five-digit integer divider. Light emitting diode displays input values, use 7-segment display displays the resulting decimal result. Dividend and dividend in two inputs, when typing in the divisor and divid...

111 classic instances of Verilog

Verilog HDL is a hardware description language used to countLaw level, the structure level, gate-level switch level a variety of abstract designHierarchy modeling of digital systems. the complexity of system objects by modeling of digital switchesCircuit (for example, PMOs/NMOS), simple (for exam...

reconfigurable control unit

A verilog code to scale pixels using reconfigurable control unit. we wll take image pixels as input and process them using the logic and will give the output....


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