Sort by
  1. Language:Verilog
  2. Category:Algorithm
  3. Time:ALL
  4. View:All
Remove all
Language More Hide
Category More Hide

Viterbi decoder 2-1-7

viterbi decoding algorithm is a decoding algorithm for convolutional codes. Advantages not say. Drawback is bound to increase with the complexity of the algorithm is to increase the length of the fast. N is the path length constraint 7:00 to compare 64 there, the path goes to 8:00 128. (2 << (...

FPGA implementation of QPSK modulation and demodulation algorithm code

The algorithm for QPSK modulation and demodulation carrier using Costas-loop synchronization algorithm, algorithm for bit timing by Gardner...

OFDM implementation of FPGA algorithm

Application backgroundCyclone 4 on OFDM algorithm, the carrier number 64, the source bit PN9 1.024Mbit/s pseudo random sequence, the first 4bit a group through the symbol mapping module map 16QAM symbol, a set of 64 symbols for IFFT operations, the results of serial output, through the digital outpu...

Verilog code for RS encoding and decoding


Viterbi Convolutional coding and decoding algorithm for FPGA realization of the project

Convolutional coding uses 2,1,2 non-systematic Convolutional codes, decoding algorithm using the Viterbi algorithm, absolute engineering validation systems; supports up to 50Mbit/s more throughput...

Verilog language implementation of AES advanced encryption algorithms

&Nbsp;AES Verilog language implementation of advanced encryption algorithms...

jpeg encoder on fpga

here jpeg encoder with dct is presented The representation of the colors in the image is converted from RGB to Y′CBCR, consisting of one luma component (Y'), representing brightness, and two chroma components, (CB and CR), representin...

1024 pipelined FFT algorithm

FFT discrete Fast Fourier transform algorithm, a signal can be transformedTo the frequency domain. Is difficult to see what some signals in the time domain characteristics, but transformed to the frequency domain, it is easy to see that feature. This is the reason why many signal analysis based on F...

DDC DDC design Verilog

DDC DDC design Verilog source code, after the actual validation. The values obtained by table look-up method COS,sin, ROM COS.v, Sin.v DDS direct digital frequency, digital down-converter. And VHDL source code;Worth doing RF baseband reference, requires some knowledge of software-defined radio....

FPGA driver VGA display pictures

FPGA drive VGA display pictures of the complete code, tests available, RGB information has been saved in the ROM have a picture, you can change the picture, extraction programs can go online to download a RGB, RGB information stored in ROM image-FPGAVGA CODE...

prev 1 2 3 4 5 next


Don't have an account? Register now
Need any help?
Mail to:


CodeForge Chinese Version
CodeForge English Version

Where are you going?

^_^"Oops ...

Sorry!This guy is mysterious, its blog hasn't been opened, try another, please!

Warm tip!

CodeForge to FavoriteFavorite by Ctrl+D