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Viterbi decoder 2-1-7

viterbi decoding algorithm is a decoding algorithm for convolutional codes. Advantages not say. Drawback is bound to increase with the complexity of the algorithm is to increase the length of the fast. N is the path length constraint 7:00 to compare 64 there, the path goes to 8:00 128. (2 << (...

FPGA implementation of QPSK modulation and demodulation algorithm code

The algorithm for QPSK modulation and demodulation carrier using Costas-loop synchronization algorithm, algorithm for bit timing by Gardner...

OFDM implementation of FPGA algorithm

Application backgroundCyclone 4 on OFDM algorithm, the carrier number 64, the source bit PN9 1.024Mbit/s pseudo random sequence, the first 4bit a group through the symbol mapping module map 16QAM symbol, a set of 64 symbols for IFFT operations, the results of serial output, through the digital outpu...

Verilog code for RS encoding and decoding


Verilog language implementation of AES advanced encryption algorithms

&Nbsp;AES Verilog language implementation of advanced encryption algorithms...

AES algorithm Verilog code

Application backgroundAES encryption algorithm, Encryption Standard Advanced (AES), also known as the Rijndael encryption method, is a block encryption standard used by the federal government. This standard is used to replace the original DES, has been analyzed and widely used in the world. After fi...

HDMI display

About HDMI display, Verilog language, with 1280*720 resolution, different images can be achieved by adding your own logic, specific uses described in the annex, HDMI display SiI9134 driver chip, very good compatibility with different data formats....


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