▍OV7670 driver
This code is sdram vga controller with ov7670 display. Welcome to download and try. Thank you for your support....
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▍DDR2 controller Verilog
Application backgroundVerilog language DDR2 controller, mainly through the control of the user interface control DDR2 DDR2 read and write, this program is to complete a simple write address, write data to DDR2, and then write the address, read data back, to verify the DDR2 read and write.Key Technol...
▍AD7091R driver (FPGA)
Application backgroundCode is on the Internet to find, and recently to see the DAC and ADC driver, the feeling can also be shared to everyone, I think for the understanding of ADCAnd the working principle of DAC also helps....
▍Stepper motor control simulation with MODELSIM VERILOG programs all
VERILOG programs with full simulation of step-motor vector (in MODELSIM6 simulation of all), you can directly use to design applications using LATTICE,ALTERA, or XILINX chip select. you can also modify the source code to meet your design requirements...
▍UART Verilog code
Including uart baud rate selected transceiver and the underlying file, use any FPGA, proven verilog code....
▍FPGA USB driver
Application backgroundIs the very first officially available release of the core This- is still under active development It- do not modify the sources Please!- that are not implemented yet or, are known not to work yet: Things - line/link control interface is not implemented yet. This includes...
▍fpga spi wishbone
fpga spi wishbone,verilog modify,it was test ok!wishbone is not is bieging!...
▍Verilog code for SDRAM
SDRAM driver, written in the Verilog language, Verilog reference those things is coming from, and is divided into three modules, initialize the module, the function module and the control module, the module which has a total of three modules together. 4bank row width column widths are 12-8-bit SDRAM...
▍AD7766-driven, FPGA,VERILOG
AD7766 drive, drive frequency is the highest 128k, 24MHz Board clock, after the PLL divider input driver, the program on the Altera Cyclone IVE verified; simulation files...
▍SDRAM test FPGA
Application backgroundDRAM, is dynamic random-access memory synchronous (dynamic random access memory) for short. There is a synchronous interface for dynamic random access memory (DRAM). Usually, there is an asynchronous interface with the DRAM, so it can always respond to the change of the input.....
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