▍The DMAC module in AMBA Bus based on SOC design
This design is based on the SOC system, using AMBA Bus DMA data transfer mode control module design of DMAC, a total of five modules, proven design timing constraints and other requirements...
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▍Ethernet communication design Siga-S16FPGA Development Board
Siga-S16 based on Xilinx Spartan6 XC6SLX16 FPGA Development Board Ethernet communications. This test comes back to form, namely FPGA accepted process to PC (computer) sends UDP packets to resolve destination Mac address to determine if this is the packet to the FPGA. If that is the case, put the pac...
▍Collected some foreign Classical Verilog code
Collection of some foreign classic Verilog code, very classic, practical, suitable for some Verilog programming experience in the habit of learning. There are some notes of intermediate, easy to understand and analysis, very good use. Some examples of the classic, learning together, encourage each o...
▍Verilog use VGA display to push the box game
Application backgroundUsing FPGA to design the classic push box game, in the film on the chip ROM storage material and through the drive VGA display to achieve the game interface, players can control the game through the PS2 keyboard keys to control the case, when all the boxes arrive at the end of...
▍GPSR(Homemade GPS Receiver)
I was motivated to design this receiver after reading the work of Matjaž Vidmar, S53MV, who developed a GPS receiver from scratch, using mainly discrete components, over 20 years ago. His use of DSP following a hard-limiting IF and 1-bit ADC interested me. The receiver described here works on the s...
▍Ethernet for FPGA-PC communication
Description: This projectwas to design an interface that enabled the FPGA board to communicate withother devices via the on-board Ethernet connection.Responsibility: Design of 10Base T Ethernet MAC has been done in verilog and implemented the same onSpartan 3E FPGA Board. ...
▍Zybo_audio
Application backgroundThis is a zybo based audio player code, you can achieve audio capture and playbackKey TechnologyAudio capture and playback, based on Verilog language embedded development...
▍I2C verilog code
So this is my second attempt to write the I2C protocol and I have learned a few important things. I believe I am very close to getting this working but have gotten to a point where I have no clue what I may be doing wrong. I have set up 3 indicators to test for slave acknowledgements and 3...
▍Verilog simulation of digital stopwatch for source
1 ． 具有暂停/启动功能；2． With resume function;3. 6 digital tube display hundreds of seconds, seconds and minutes. Solution : On request, using a bottom-up design approach, opting for max+plus2 For editing and debugging. The whole is divided into two sections: one is co...
▍Asynchronous FIFO
It is very important to understand the signal stability when controlling communication betweensystems with different clocks, since for a traveling signal the new clock domain appears to beasynchronous. If the signal is not synchronized to new clock the first storage element of the newclock domain ma...
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