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GPSR(Homemade GPS Receiver)

family:Verdana, Arial, Helvetica, sans-serif;font-size:13.6000003814697px;line-height:20px;white-space:normal;"> 我积极地设计此接收器后阅读的工作 的维德马尔 Matjaž,S53MV,开发一个 GPS 接收器,从零开始,使用主要分立元件,在 20 多年前了他对 DSP...

Ethernet for FPGA-PC communication

size:16px;">描述: 这个项目是设计启用 FPGA 板交流构筑设备通过板载以太网连接的界面。岗位职责: 设计的 10Base T 以太网 MAC 一直做的 verilog 和执行相同的 onSpartan 3E FPGA 板。...

Verilog simulation of digital stopwatch for source

align:left;text-indent:21pt;" align="left"> 1.具有暂停/启动功能;2.具有重新开始功能;3.用6个数码管分别显示百分秒、秒和分钟。 Solution:根据要求,采用自底向上的设计方法:选择了max+plus2进行编辑和调试。 整体来说...

Design and realization of digital cymometer based on Verilog HDL

Design and realization of digital cymometer based on Verilog HDL, complete engineering documents, the design meets the following requirements:(1) digital display frequency values(2) measuring deviation is less than 0.1%(3) testing of sine or square wave signal for the following 10kHz(4) square wave...

AES 256 encryption engine, 4 input pipeline

output target-output" style="margin: 0px 0px 5px; padding: 0px; line-height: 22px; font-size: 14px; color: rgb(51, 51, 51); font-family: arial;">本代码是一种实现AES-256。此代码加密4种不同的输入数据的128位与4个不同的密钥256位为每个数据所有加密的数据产生67...

Camera acquisition process (Verilog)



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