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64point sdf fft

space:normal;">基4的64点SDF结构,采用基4的流水线的结构,速度快,存储资源使用的少,方便在FPGA上实现,...

Asynchronous FIFO

size:16px;">这是非常重要的理解通信控制信号时的稳定性不同的时钟系统,由于移动信号的新时钟域似乎是异步。如果信号不同步的新的时钟的第一存储元件时钟域可到亚稳态和最坏的情况是,解决时间不能预测。它可以遍历整个...

Ac97_rtl (AC97 2 common criteria program)

1, AC97, 2, can be used to simulate the source; 2, RTL, as well as the testbench code; 3, from the network to learn; 4, AC97 is a common standard, this control code will be more and more engineers will focus on, looking forward to your continuous improvement; 5, deficiencies,...

pulse width modulator

space:nowrap;">脉宽调制 (PWM) 或脉冲宽度调制 (PDM) 是一种调制技术, 确认的脉冲宽度正式的脉冲持续时间,基于调制器信号信息。 尽管这种调制技术可以用来编码信息的传输,它的主要用途 是允许控制的电气设备,...

Water light Verilog source code

This program is the original water light program, good for beginners to learn, using programs written in Verilog. Mobile led the experiment....

Custom IP-FIFO

size:16px;">该程序模块详细介绍了自定义缓存模块FIFO的设计过程,正在学习自定义FIFO模块并挂载在avalon总线上用作缓存的读者可参考该程序。...

My First FPGA

size:14px;color:#000000;">这是一个简单的项目,为使用 DE2I 150 板。 DE2i 150 配备的实际硬件迂回和知识产权,以及车载多媒体外设,重构的终极灵活性的大约 150 K 逻辑元素为一个真正的系统就绪解决方案为任何任务的可扩展性选项。...

Verification of AND gate in system verilog

size:16px;">Description: To prepare aclass based layered test bench environment in SystemVerilog (SV) to verify a simple AND gateResponsibility: All the parts of testbench(Transaction, Generator/ Sequencer, BFM/Driver, Interface, Monitor, Checker/ Scoreboard,Agent and Environment) is developed in Sy...

Manchester decoding

get install gplcver gtkwave##运行仿真 ;美元过分的人。T V人。 ;gtkwave美元verilog.dump ; ;读取保存文件:gtksetup.sav#...

3E cp132 Spartan counter

Application backgroundPeople need counters in order to keep track of states and other valuable data. In embedded systems, accurate timing is also highly valued. Thus, this basic application of a counter will allow for a person to expand it for other devices they may use.     ...


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