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High efficiency LDPC code encoder FPGA development, VerilogHDL, and MATLAB simulation

Application backgroundWIMAX standard uses LDPC code as its optional channel encoding program. The WIMAX standard is the fourth global 3G standard for ITU, WCDMA, CDMA200, and TD-SCDMA in 2007. LDPC code with its excellent error correction performance has become a hot research topic in recent years....

Verilog HDL design and development laboratory

The most detailed collection of Verilog examples, rapid entry to the master. As an experimental tutorial this tutorial is divided into two parts: the FPGA hardware system based on Verilog and advanced interface design experiments. For the beginner can quickly get started. For those who have come int...

Complete SD controller! Supported file systems.

32-bit Wishbone Interface • DMA • Buffer Descriptor • Compliant with SD Host Controller Spec version 2.0 • Support SD 4-bit mode • Interrupt-on-completion of Data and Command transmission • Write/Read FIFO with variable size • Internal implementation of CRC16 for data lines and...

ADPLL Design and Implementation on FPGA

This paper presents the ADPLL design using Verilog and its implementation on FPGA.ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulatingVerilog Code. This paper gives details of the basic blocks of an ADPLL. In this paper,implementation of ADPLL is described in detail....

FPGA implementation of 16QAM modulation and demodulation

The source code is to achieve 14-way parallel 16QAM modulation and demodulation, which also includes test files, has been in the top altera FPGA implements its validity, can be directly used to use....

floating point adder

verilog code coded in xilinx used to add 2 floating point numbers.... and the technique used in this coding is piplining........

FPGA DDS generators

DE2 development platform, uses the Veriolg language programming realized DDS signal output, frequency and step wave output with adjustable using Modelsim and FPGA embedded logic Analyzer verifies the correctness of design, can meet the needs of engineering....

Double precision floating point core Verilog

Application backgroundIEEE-754 compliant double-precision floating point unit. 4 operations (addition, subtraction, multiplication, division) are supported, as are the 4 rounding modes (nearest, 0, +inf, -inf). This unit also supports denormalized numbers, which is rare because most floating point u...

Asynchronous clock domain crossing fifo design

Asynchronous clock domain crossing design a FIFO fifo design is one of the most common problems encountered by ASIC designers. This article focuses on howSample design FIFO-- This is a deceptively simple but complex task. The outset, we should note, FIFO is typically used transition clock domai...

Ethernet 10GE MAC

The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae. ...

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