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12 MIPS instruction cycle CPU design "ISE implementation"

12 MIPS instruction number 9 basic instruction cycle CPU design plus an additional three instruction contact email jar,Lui,Jr xiuchuantangxi@126.com "ISE implementation"...

Uart2bus_latest.tar

Application backgroundBased on Verilog serial interface control module, a detailed description of the document and test module, with a good learning value. Can be applied in the field of industrial control, communications. Based on Verilog serial interface control module, a detailed description of t...

PCIe DMA Xilinx reference routines

Application backgroundXilinx PCIe xapp1022 reference,; Xilinx PCIe xapp1022 reference,; Xilinx PCIe xapp1022 reference,; Xilinx PCIe reference, xapp1022Key TechnologyFpga+pcie Xilinx data acquisition card, including Linux and windows driver and test program fpga+ PCIe data acquisition card including...

Controller SDRAM

Application backgroundController RTL for the SDRAM level, by reading and writing state machine control, due to the SDRAM clock for verification of the maximum 133MHz, it uses 100MHz rate to write SDRAM, and then the SDRAM data into the FIFO, and then read from the FIFO data, displayed on the digital...

NIOS and DM9000A engineering based on II ISP1362

Application backgroundISP1362 and DM9000A projects based on II SOPC NIOS. Application software QUARTUS, IDE....


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