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Ethernet ip core verilog realization

Ethernet (Ethernet) Verilog IP core written in verilogHDL language Ethernet soft core, and Ethernet which helps a lot for learning Verilog language....

Verilog implementation of UDP protocol

Verilog implementation of UDP protocol can be used, including protocols such as subparagraph ARP,UDP,IP, for TCP/IP protocols using FPGA's people, should get in the mobile help...


10m/100m/1000m source full version, and achieved under the three models of the Mac,Verilog code, and reference documentation!...

Sfp to Eternet transfer data

Code for ML-605 xilinx board, with extention board S14-S (4sfp ports). Project for transfer data from optical line to sfp-module to rj-45 ethernet and receiving on PC. Using Virtex-6 Tri-Mode Ethernet MAC Wrapper.PC1 (Ethernet)-> media converter (1,25Gb/s) -> optical line -> sfp-module(1,25...

Netmagic demonstration project: Ping IP package to test the bypass between the port and the port or through the mode

Application backgroundThe UM module includes four interface: input_ctrl, output_ctrl, ML, and DDR2 interface. The UM input_ctrl and output_ctrl interfaces are used to receive packets from CDP input_ctrl module and transmit packets to CDP output_ctrl module. Eight UM ID registers and eight UM RA...


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