dct2d.txt ( File view )

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module dct2d ( CLK, RST, xin,dct_2d,rdy_out);
output [11:0] dct_2d;
input CLK, RST;
input[7:0] xin; // input
output rdy_out;
wire[11:0] dct_2d;

//multipliers coefficients

reg[7:0] mul_coef1a, mul_coef2a, mul_coef3a, mul_coef4a;

//dct1d 

reg[7:0] xa0_in, xa1_in, xa2_in, xa3_in, xa4_in, xa5_in, xa6_in, xa7_in;
reg[8:0] xa0_reg, xa1_reg, xa2_reg, xa3_reg, xa4_reg, xa5_reg, xa6_reg, xa7_reg;
reg[7:0] add_sub1a_abs,add_sub2a_abs,add_sub3a_abs,add_sub4a_abs;
reg[9:0] add_sub1a,add_sub2a,add_sub3a,add_sub4a;
reg sign1a, sign2a, sign3a, sign4a;
reg[18:0] product1a,product2a,product3a,product4a;
wire[35:0] product1a_all,product2a_all,product3a_all,product4a_all;
reg[1:0] i_wait;
reg add_sub_selecta;
reg[18:0] z_out_int1,z_out_int2;
reg[18:0] z_out_int;
wire[10:0] z_out_rnd;
wire[10:0] z_out;
integer indexi;

// counters
reg[3:0] counter14 ;
reg[3:0] counter8;
reg[6:0] counter79;
reg[6:0] wr_counter,rd_counter;
reg[6:0] counter92;

// memory
reg[10:0] data_out;
wire en_ram1,en_dct2d;
reg en_ram1reg,en_dct2d_reg;
reg[10:0] ram1_mem[63:0],ram2_mem[63:0]; 
                                        

//dct2d  
wire[10:0] data_out_final;
reg[10:0] xb0_in, xb1_in, xb2_in, xb3_in, xb4_in, xb5_in, xb6_in, xb7_in;
reg[11:0] xb0_reg, xb1_reg, xb2_reg, xb3_reg, xb4_reg, xb5_reg, xb6_reg, xb7_reg;
reg[11:0] add_sub1b,add_sub2b,add_sub3b,add_sub4b;
reg[10:0] addsub1b_abs,addsub2b_abs,addsub3b_abs,addsub4b_abs;
reg sign1b, sign2b,sign3b, sign4b;
reg[19:0] product1b,product2b,product3b,product4b;
wire[35:0] product1b_all,product2b_all,product3b_all,product4b_all;
reg add_sub_selectb;
reg[19:0] dct2d_int1,dct2d_int2;
reg[19:0] dct_2d_int;
wire[11:0] dct_2d_rnd;


//dct1d begin


// determining the multipliers coefficients.if a coefficient is negative the 7th bit of it is 1  
always @ (posedge RST or posedge CLK)
 begin
if (RST)
begin
 mul_coef1a <= 8'd0;
 mul_coef2a <= 8'd0;
 mul_coef3a <= 8'd0;
 mul_coef4a <= 8'd0;
end
else
begin
case (indexi)
  0 : begin
      mul_coef1a <= 8'd91; 
      mul_coef2a <= 8'd91; 
      mul_coef3a <= 8'd91; 
      mul_coef4a <= 8'd91;
      end
                   
 1 : begin 
       mul_coef1a <= 8'd126; 
       mul_coef2a <= 8'd106;  
       mul_coef3a <= 8'd71;  
       mul_coef4a <= 8'd25;
       end
 2 : begin
       mul_coef1a <= 8'd118; 
       mul_coef2a <= 8'd49;  
       mul_coef3a[7] <= 1'b1; mul_coef3a[6:0] <= 7'd49; 
       mul_coef4a[7] <= 1'b1; mul_coef4a[6:0] <= 7'd118;
       end
 3 : begin
       mul_coef1a<= 8'd106; 
       mul_coef2a <= 1'b1; mul_coef2a [6:0] <= 7'd25; 
       mul_coef3a[7] <= 1'b1; mul_coef3a[6:0] <= 7'd126; 
       mul_coef4a[7] <= 1'b1; mul_coef4a[6:0] <= 7'd71;
       end
4 : begin 
       mul_coef1a <= 8'd91; 
       mul_coef2a <= 1'b1; mul_coef2a[6:0] <= 7'd91; 
       mul_coef3a[7] <= 1'b1; mul_coef3a[6:0] <= 7'd91;
       mul_coef4a <= 8'd91;
       end
5 : begin 
       mul_coef1a <= 8'd71; 
	   mul_coef2a[7] <= 1'b1;mul_coef2a[6:0] <= 7'd126; 
       mul_coef3a <= 8'd25;   
       mul_coef4a <= 8'd106;
       end
6 : begin 
       mul_coef1a <= 8'd49; 
       mul_coef2a[7] <= 1'b1; mul_coef2a[6:0] <= 7'd118; 
       mul_coef3a <= 8'd118;  
       mul_coef4a[7] <= 1'b1; mul_coef4a[6:0] <= 7'd49;
       end
7 : begin
       mul_coef1a <= 8'd25;  
       mul_coef2a <= 1'b1;mul_coef2a[6:0] <= 7'd71;
       mul_coef3a <= 8'd106;  
       mul_coef4a[7] <= 1'b1; mul_coef4a[6:0] <= 7'd126;
       end
       endcase
       end
end


// 8-bit input shifts 8 times 
always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       xa0_in <= 8'b0;
       xa1_in <= 8'b0;
       xa2_in <= 8'b0;
       xa3_in <= 8'b0;
       xa4_in <= 8'b0;
       xa5_in <= 8'b0;
       xa6_in <= 8'b0; 
       xa7_in <= 8'b0;
       end
   else
       begin
       xa0_in <= xin;
       xa1_in <= xa0_in;
       xa2_in <= xa1_in;
       xa3_in <= xa2_in;
       xa4_in <= xa3_in;
       xa5_in <= xa4_in;
       xa6_in <= xa5_in;
       xa7_in <= xa6_in;
       end
   end

// shifted inputs are registered every 8th clk using counter8(the registration happens whenever a row is complete)

always @ (posedge CLK or posedge RST)
begin
    if (RST)
        begin
        counter8 <= 4'b0;
        end
	else if (counter8 < 4'b1000)
	     begin
	     counter8 <= counter8 + 1;
	     end
    else 
         begin
         counter8 <= 4'b0001;
         end
end

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       xa0_reg <= 9'b0;
       xa1_reg <= 9'b0;
       xa2_reg <= 9'b0; 
       xa3_reg <= 9'b0;
       xa4_reg <= 9'b0;
       xa5_reg <= 9'b0; 
       xa6_reg <= 9'b0;
       xa7_reg <= 9'b0;
       end
   else if (counter8 == 4'b1000)
       begin 
       xa0_reg <= {
xa0_in[7],xa0_in
};
       xa1_reg <= {
xa1_in[7],xa1_in
}; 
       xa2_reg <= {
xa2_in[7],xa2_in
};
       xa3_reg <= {
xa3_in[7],xa3_in
};
       xa4_reg <= {
xa4_in[7],xa4_in
}; 
       xa5_reg <= {
xa5_in[7],xa5_in
}; 
       xa6_reg <= {
xa6_in[7],xa6_in
};
       xa7_reg <= {
xa7_in[7],xa7_in
};
       end
   else 
       begin
       end
   end

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       add_sub_selecta <= 1'b0;
       end
   else 
       begin 
       add_sub_selecta <= ~add_sub_selecta;
       end
   end


// adder_ subtractor block.add_sub_selecta is used to select the operation add or sub

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       add_sub1a <= 10'b0;
       add_sub2a <= 10'b0;
       add_sub3a <= 10'b0; 
       add_sub4a <= 10'b0;
       end
   else
       begin
       if (add_sub_selecta == 1'b1)
	         begin
           add_sub1a <= (xa7_reg + xa0_reg); 
           add_sub2a <= (xa6_reg + xa1_reg);
           add_sub3a <= (xa5_reg + xa2_reg); 
           add_sub4a <= (xa4_reg + xa3_reg);
           end
       else if (add_sub_selecta == 1'b0)
	         begin
	       add_sub1a <= (xa7_reg - xa0_reg); 
           add_sub2a <= (xa6_reg - xa1_reg);
           add_sub3a <= (xa5_reg - xa2_reg); 
           add_sub4a <= (xa4_reg - xa3_reg);
	         end
       end
   end



//wait counter

always @ (posedge RST or posedge CLK)
   begin
   if (RST)
       begin
       i_wait <= 2'b01;
       end
   else  if (i_wait != 2'b00)
      begin
      i_wait  <= i_wait - 1;
      end
   else
      begin
      i_wait  <= 2'b00;
      end
   end

// First valid add_sub appears at the 10th clk 


always @ (posedge RST or posedge CLK)
begin
    if (RST)
       begin  
         add_sub1a_abs<= 9'b0;
         sign1a <= 1'b0;
       end
    else 
       begin
       case (add_sub1a[9])
       1'b0: begin 
              add_sub1a_abs <= add_sub1a;
              sign1a <= 1'b0; 
              end
       1'b1: begin 
              add_sub1a_abs <= (-add_sub1a) ;
              sign1a <= 1'b1; 
              end 
       endcase
       end
end

always @ (posedge RST or posedge CLK)
begin
    if (RST)
       begin  
         add_sub2a_abs <= 9'b0;
         sign2a <= 1'b0;
       end
    else 
       begin
       case (add_sub2a[9])
       1'b0: begin 
              add_sub2a_abs <= add_sub2a;
              sign2a <= 1'b0;
              end
       1'b1: begin 
              add_sub2a_abs <= (-add_sub2a) ;
              sign2a <= 1'b1; 
              end 
       endcase
       end
end

always @ (posedge RST or posedge CLK)
begin
    if (RST)
       begin  
         add_sub3a_abs <= 9'b0;
         sign3a <= 1'b0; 
       end
    else 
       begin
       case (add_sub3a[9])
       1'b0: begin 
              add_sub3a_abs<= add_sub3a;
              sign3a <= 1'b0; 
              end
       1'b1: begin 
              add_sub3a_abs <= (-add_sub3a);
              sign3a <= 1'b1; 
              end 
       endcase
       end
end

always @ (posedge RST or posedge CLK)
begin
    if (RST)
       begin  
         add_sub4a_abs <= 9'b0;
         sign4a <= 1'b0; 
       end
    else 
       begin
       case (add_sub4a[9])
       1'b0: begin 
              add_sub4a_abs <= add_sub4a;
              sign4a <= 1'b0; 
              end
       1'b1: begin 
              add_sub4a_abs <= (-add_sub4a);
              sign4a <= 1'b1; 
              end 
       endcase
       end
end

     assign product1a_all = add_sub1a_abs * mul_coef1a[6:0];
     assign product2a_all = add_sub2a_abs * mul_coef2a[6:0];
     assign product3a_all = add_sub3a_abs * mul_coef3a[6:0];
     assign product4a_all = add_sub4a_abs * mul_coef4a[6:0];



always @ (posedge RST or posedge CLK)
  begin
    if (RST)
      begin
        product1a <= 18'b0;
        product2a <= 18'b0; 
        product3a <= 18'b0;
        product4a <= 18'b0; indexi<= 7;
      end // determining  the products sign
    else if (i_wait == 2'b00)
      begin
   
        
        product1a <= (sign1a ^ mul_coef1a[7]) ? (-product1a_all[15:0]) :(product1a_all[15:0]);
        product2a <= (sign2a ^ mul_coef2a[7]) ? (-product2a_all[15:0]) :(product2a_all[15:0]);
        product3a <= (sign3a ^ mul_coef3a[7]) ? (-product3a_all[15:0]) :(product3a_all[15:0]);
        product4a <= (sign4a ^ mul_coef4a[7]) ? (-product4a_all[15:0]) :(product4a_all[15:0]);
        

        if (indexi == 7)
            indexi <= 0;
        else // using indexi next set of coefficients are selected for each row. indexi is incremented every 10th clk  whenever i_wait is 0
           indexi <= indexi + 1;
        end
  end



// final adder. Adding the ouputs of the 4 multipliers 

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       z_out_int1 <= 19'b0;
       z_out_int2 <= 19'b0;
       z_out_int  <= 19'b0;
       end
   else
       begin
       z_out_int1 <= (product1a + product2a);
       z_out_int2 <= (product3a + product4a);
       z_out_int <= (z_out_int1 + z_out_int2);
       end
   end

// rounding 

assign z_out_rnd = z_out_int[7] ? (z_out_int[18:8] + 1'b1) : z_out_i
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