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Serial.cpp - One of the basics of Verilog source code


						
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NameSizeDate
 count.cr.mti660.00 B18-10-13 19:21
 count.mpf38.00 B18-10-13 19:21
 count4.v248.00 B17-10-13 21:25
 count4.v.bak247.00 B17-10-13 21:25
 test.v316.00 B17-10-13 21:23
 test.v.bak315.00 B17-10-13 21:23
 vsim.wlf32.00 kB17-10-13 21:40
 _info422.00 B18-10-13 19:21
 _primary.dat371.00 B18-10-13 14:25
 _primary.vhd236.00 B18-10-13 19:21
 _primary.dat327.00 B18-10-13 14:25
 _primary.vhd62.00 B18-10-13 14:25
 <count4>0.00 B18-10-13 19:52
 <t>0.00 B18-10-13 19:52
 <_temp>0.00 B17-10-13 21:18
 <work>0.00 B18-10-13 19:52
 <count>0.00 B18-10-13 19:52
...
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