display.v ( File view )

  • By ketaopku 2013-11-24
  • View(s):33
  • Download(s):2
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			module display (
clk_state,
clk_timer,
clk_reg,
rest,
numx,
numy,
data,
wl);

input clk_state;
input clk_timer;
input clk_reg;
input rest;
input numx;
input numy;
output [7:0] data;
output [7:0] wl;

reg [1:0] sd0;
reg [7:0] wl;
reg [7:0] data;
wire [5:0] numx;//count number
wire [5:0] numy;
wire [7:0] dataxh,dataxl,datayh,datayl;


///*parameter t_state_s0=18;//the time of state_s0 18'
//parameter t_state_s1=3;
//parameter t_state_s2=10;
//parameter t_state_s3=2;
//parameter t_state_s4=18;
//parameter t_state_s5=10;
//parameter t_state_s6=3;
//parameter t_state_s7=2;*/

parameter slct0 = 8'b01110111,//assume active low
		      slct1 = 8'b10111011,
          slct2 = 8'b11011101,
          slct3 = 8'b11101110;
          


encoder a (.clk_reg(clk_reg),
            .clk_state(clk_state),
		      .time_data_in(numx),
		      .num_high(dataxh),
	       	.num_low(dataxl));
encoder b (.clk_reg(clk_reg),
        .clk_state(clk_state),
		      .time_data_in(numy),
		      .num_high(datayh),
		      .num_low(datayl));
		
		

always@( posedge clk_state or negedge rest )
begin
	if( !rest )
		begin
		wl <= 8'b11111111;
		//data <=8'b00000000;
		data <= 8'b00000000;
		sd0 <= 00;
		//numx<=3;
		//numy<=2;
		end
	else 
		case( sd0 )
			2'b00:
				begin
					wl <= slct0;
					data <= dataxh;
					sd0 <= sd0+2'b01;
				end
			2'b01:				
				begin
					wl <= slct1;
					data <= dataxl;
					sd0 <= sd0+2'b01;
				end
			2'b10:				
				begin
					wl <= slct2;
					data <= datayh;
					sd0 <= sd0+2'b01;
				end
			2'b11:				
				begin
					wl <= slct3;
					data <= datayl;
					sd0 <= sd0+2'b01;
				end
			default:
			  begin
			    sd0 <= 2'b00;
			    wl <= 8'b1111_1111;//all tubes turn off
			  end
		endcase
end
endmodule 			
...
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Name Size Date
clk_div.v1.40 kB07-11-13 13:49
clk_div.v.bak1.51 kB06-11-13 20:53
decoder.v587.00 B07-11-13 10:40
display.v1.69 kB07-11-13 11:30
display_test.v656.00 B07-11-13 11:11
encoder.v1.04 kB07-11-13 10:30
mac_test.v443.00 B06-11-13 22:32
modelsim.ini50.96 kB07-11-13 13:00
register.v1.02 kB07-11-13 09:05
reg_test.v375.00 B07-11-13 09:05
state_mach.v2.06 kB07-11-13 13:39
state_mach.v.bak2.06 kB07-11-13 13:23
test.v464.00 B07-11-13 13:42
test.v.bak527.00 B07-11-13 11:44
test_decoder.v283.00 B07-11-13 10:44
test_encoder.v433.00 B07-11-13 11:40
tr.cr.mti3.16 kB07-11-13 13:57
tr.mpf59.69 kB07-11-13 13:57
traffic_ctl.v1.26 kB07-11-13 13:43
traffic_ctl.v.bak1.25 kB07-11-13 13:42
vsim.wlf1,008.00 kB07-11-13 13:57
vopt0cca9g64.00 B07-11-13 13:00
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voptmvbj9g5.59 kB07-11-13 13:00
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vopt8k128m411.00 B07-11-13 13:17
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voptyey3ie869.00 B07-11-13 13:43
voptyfer951.79 kB07-11-13 13:42
voptyhhx7568.00 B07-11-13 13:42
_deps4.81 kB07-11-13 13:50
_primary.dat1.09 kB07-11-13 13:50
_primary.dbs3.07 kB07-11-13 13:50
_primary.vhd447.00 B07-11-13 13:50
_primary.dat810.00 B07-11-13 13:50
_primary.dbs955.00 B07-11-13 13:50
_primary.vhd257.00 B07-11-13 13:50
_primary.dat1.42 kB07-11-13 13:50
_primary.dbs2.84 kB07-11-13 13:50
_primary.vhd697.00 B07-11-13 13:50
_primary.dat1.30 kB07-11-13 13:50
_primary.dbs2.77 kB07-11-13 13:50
_primary.vhd362.00 B07-11-13 13:50
_primary.dat1.05 kB07-11-13 13:50
_primary.dbs1.73 kB07-11-13 13:50
_primary.vhd722.00 B07-11-13 13:50
_primary.dat1.79 kB07-11-13 13:50
_primary.dbs3.29 kB07-11-13 13:50
_primary.vhd411.00 B07-11-13 13:50
_primary.dat688.00 B07-11-13 13:50
_primary.dbs1.42 kB07-11-13 13:50
_primary.vhd64.00 B07-11-13 13:50
_primary.dat508.00 B07-11-13 13:50
_primary.dbs1,003.00 B07-11-13 13:50
_primary.vhd64.00 B07-11-13 13:50
_primary.dat485.00 B07-11-13 13:50
_primary.dbs817.00 B07-11-13 13:50
_primary.vhd68.00 B07-11-13 13:50
_primary.dat432.00 B07-11-13 13:50
_primary.dbs826.00 B07-11-13 13:50
_primary.vhd74.00 B07-11-13 13:50
_primary.dat372.00 B07-11-13 13:50
_primary.dbs676.00 B07-11-13 13:50
_primary.vhd80.00 B07-11-13 13:50
_primary.dat494.00 B07-11-13 13:50
_primary.dbs1.01 kB07-11-13 13:50
_primary.vhd80.00 B07-11-13 13:50
_primary.dat869.00 B07-11-13 13:50
_primary.dbs1.84 kB07-11-13 13:50
_primary.vhd371.00 B07-11-13 13:50
_info3.39 kB07-11-13 13:50
_vmake26.00 B07-11-13 13:50
<@_opt>0.00 B07-11-13 13:24
<@_opt1>0.00 B07-11-13 13:17
<@_opt2>0.00 B07-11-13 13:50
<clk_div>0.00 B07-11-13 13:50
<decoder>0.00 B07-11-13 13:50
<display>0.00 B07-11-13 13:50
<encoder>0.00 B07-11-13 13:50
<register>0.00 B07-11-13 13:50
<state_mach>0.00 B07-11-13 13:50
<t1>0.00 B07-11-13 13:50
<t2>0.00 B07-11-13 13:50
<test>0.00 B07-11-13 13:50
<testreg>0.00 B07-11-13 13:50
<te_decoder>0.00 B07-11-13 13:50
<te_encoder>0.00 B07-11-13 13:50
<traffic_ctl>0.00 B07-11-13 13:50
<_temp>0.00 B07-11-13 13:50
<work>0.00 B07-11-13 13:57
<wkt>0.00 B07-11-13 13:57
...
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display.v (769.16 kB)

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