modelsim.ini ( File view )

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			; Copyright 1991-2009 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;   

[Library]
others = $MODEL_TECH/../modelsim.ini
;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers       // Source files only for this release
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
;mvc_lib = $MODEL_TECH/../mvc_lib

work = work
[vcom]
; VHDL93 variable selects language version as the default. 
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
; Value of 3 or 2008 for VHDL-2008
VHDL93 = 2002

; Show source line containing error. Default is off.
; Show_source = 1

; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0

; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0

; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0

; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0

; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0

; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0

; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1

; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1

; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1

; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1

; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0

; Turn off PSL assertion warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0

; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0

; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1

; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1

; Treat as errors:
;   case statement static warnings
;   warnings caused by aggregates that are not locally static
; Overrides NoCaseStaticError, NoOthersStaticError settings.
; PedanticErrors = 1

; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1

; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1

; Turn on some limited synthesis rule compliance checking. Checks only:
;    -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1

; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1

; Turns on lint-style checking.
; Show_Lint = 1

; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1

; Perform default binding at compile time.
; Default is to do default binding at load time.
; BindAtCompile = 1;

; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1

; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1

; Run the 0-in compiler on the VHDL source files
; Default is off.
; ZeroIn = 1

; Set the options to be passed to the 0-in compiler.
; Default is "".
; ZeroInOptions = ""

; Turn on code coverage in VHDL design units. Default is off.
; Coverage = sbceft

; Turn off code coverage in VHDL subprograms. Default is on.
; CoverageSub = 0

; Automatically exclude VHDL case statement default branches. 
; Default is to not exclude.
; CoverExcludeDefault = 1

; Control compiler and VOPT optimizations that are allowed when
; code coverage is on.  Refer to the comment for this in the [vlog] area. 
; CoverOpt = 3

; Inform code coverage optimizations to respect VHDL 'H' and 'L'
; values on signals in conditions and expressions, and to not automatically
; convert them to '1' and '0'. Default is to not convert.
; CoverRespectHandL = 0

; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a VHDL condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192

; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192

; Enable or disable Focused Expression Coverage analysis for conditions and
; expressions. Focused Expression Coverage data is provided by default when
; expression and/or condition coverage is active.
; CoverFEC = 0

; Enable or disable short circuit evaluation of conditions and expressions when
; condition or expression coverage is active. Short circuit evaluation is enabled
; by default.
; CoverShortCircuit = 0

; Use this directory for compiler temporary files instead of "work/_temp"
; CompilerTempDir = /tmp

; Add VHDL-AMS declarations to package STANDARD
; Default is not to add
; AmsStandard = 1

; Range and length checking will be performed on array indices and discrete
; ranges, and when violations are found within subprograms, errors will be
; reported. Default is to issue warnings for violations, because subprograms
; may not be invoked.
; NoDeferSubpgmCheck = 0

; Turn off detection of FSMs having single bit current state variable.
; FsmSingle = 0

; Turn off reset state transitions in FSM.
; FsmResetTrans = 0

[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1

; Turn on `protect compiler directive processing.
; Default is to ignore `protect directives.
; Protect = 1

; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1

; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1

; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1

; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1

; Turns on lint-style checking.
; Show_Lint = 1

; Show source line containing error. Default is off.
; Show_source = 1

; Turn on bad option warning. Default is off.
; Show_BadOptionWarning = 1

; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
; vlog95compat = 1

; Turn off PSL warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0

; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0

; Set the threshold for automatically identifying sparse Verilog memories.
; A memory with depth equal to or more than the sparse memory threshold gets
; marked as sparse automatically, unless specified otherwise in source code
; or by +nosparse commandline option of vlog or vopt.
; The default is 1M.  (i.e. memories with depth equal
; to or greater than 1M are marked as sparse)
; SparseMemThreshold = 1048576 

; Set the maximum number of iterations permitted for a generate loop.
; Restricting this permits the implementation to recognize infinite
; generate loops.
; GenerateLoopIterationMax = 100000

; Set the maximum depth permitted for a recursive generate instantiation.
; Restricting this permits the implementation to recognize infinite
; recursions.
; GenerateRecursionDepthMax = 200

; Run the 0-in compiler on the Verilog source files
; Default is off.
; ZeroIn = 1

; Set the options to be passed to the 0-in compiler.
; Default is "".
; ZeroInOptions = ""

; Set the option to treat all files specified in a vlog invocation as a
; single compilation unit. The default value is set to 0 which will treat
; each file as a separate compilation unit as specified in the P1800 draft standard.
; MultiFileCompilationUnit = 1

; Turn on code coverage in Verilog design units. Default is off.
; Coverage = sbceft

; Automatically exclude Verilog case statement default branches. 
; Default is to not automatically exclude defaults.
; CoverExcludeDefault = 1

; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a Verilog condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192

; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192

; Enable or disable Focused Expression Coverage analysis for conditions and
; expressions. Focused Expression Coverage data is provided by default when
; expression and/or condition coverage is active.
; CoverFEC = 0

; Enable or disable short circuit evaluation of conditions and expressions when
; condition or expression coverage is active. Short circuit evaluation is enabled
; by default.
; CoverShortCircuit = 0


; Turn on code coverage in VLOG `celldefine modules and modules included
; using vlog -v and -y. Default is off.
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Name Size Date
clk_div.v1.40 kB07-11-13 13:49
clk_div.v.bak1.51 kB06-11-13 20:53
decoder.v587.00 B07-11-13 10:40
display.v1.69 kB07-11-13 11:30
display_test.v656.00 B07-11-13 11:11
encoder.v1.04 kB07-11-13 10:30
mac_test.v443.00 B06-11-13 22:32
modelsim.ini50.96 kB07-11-13 13:00
register.v1.02 kB07-11-13 09:05
reg_test.v375.00 B07-11-13 09:05
state_mach.v2.06 kB07-11-13 13:39
state_mach.v.bak2.06 kB07-11-13 13:23
test.v464.00 B07-11-13 13:42
test.v.bak527.00 B07-11-13 11:44
test_decoder.v283.00 B07-11-13 10:44
test_encoder.v433.00 B07-11-13 11:40
tr.cr.mti3.16 kB07-11-13 13:57
tr.mpf59.69 kB07-11-13 13:57
traffic_ctl.v1.26 kB07-11-13 13:43
traffic_ctl.v.bak1.25 kB07-11-13 13:42
vsim.wlf1,008.00 kB07-11-13 13:57
vopt0cca9g64.00 B07-11-13 13:00
vopt20dvys411.00 B07-11-13 13:24
vopt4w169g1,003.00 B07-11-13 13:00
vopt6g2rys3.29 kB07-11-13 13:24
vopta0rkys1.79 kB07-11-13 13:24
voptabbx9g508.00 B07-11-13 13:00
voptdgdhys320.00 B07-11-13 13:24
voptev0t9g452.00 B07-11-13 13:00
voptev0x363.28 kB07-11-13 13:24
vopth03eys4.67 kB07-11-13 13:24
voptibnq9g2.23 kB07-11-13 13:00
voptkgrbys12.18 kB07-11-13 13:24
voptmvbj9g5.59 kB07-11-13 13:00
_deps1.25 kB07-11-13 13:24
vopt8k128m411.00 B07-11-13 13:17
voptb4qz7m3.29 kB07-11-13 13:17
voptfkcw7m1.79 kB07-11-13 13:17
voptjb6rtj316.00 B07-11-13 13:17
voptnvvmtj2.42 kB07-11-13 13:17
vopttbhitj8.11 kB07-11-13 13:17
voptxv6ftj3.28 kB07-11-13 13:17
_deps716.00 B07-11-13 13:17
vopt0zgi0s3.35 kB07-11-13 13:50
vopt104m95316.00 B07-11-13 13:42
vopt1y9gb21.73 kB07-11-13 13:42
vopt1z6it34.81 kB07-11-13 13:42
vopt227t75817.00 B07-11-13 13:42
vopt2zjzhe864.00 B07-11-13 13:43
vopt4ezcb2257.00 B07-11-13 13:42
vopt4f6f0s10.24 kB07-11-13 13:50
vopt5f9whe2.70 kB07-11-13 13:43
vopt5fwft311.49 kB07-11-13 13:42
vopt5gsh954.62 kB07-11-13 13:42
vopt7dj6c21.05 kB07-11-13 13:42
vopt8yk9b2955.00 B07-11-13 13:42
vopt8zhct3362.00 B07-11-13 13:42
vopt90fe9512.13 kB07-11-13 13:42
vopt9hgh85485.00 B07-11-13 13:42
vopt9zyshe5.94 kB07-11-13 13:43
voptbea6b2810.00 B07-11-13 13:42
voptbx83c21.25 kB07-11-13 13:42
voptc16e85440.00 B07-11-13 13:42
voptcf78t32.77 kB07-11-13 13:42
voptfdy0c22.72 kB07-11-13 13:42
voptfyz2b2312.00 B07-11-13 13:42
voptfzw5t3697.00 B07-11-13 13:42
voptghva851.80 kB07-11-13 13:42
voptibktq13.39 kB07-11-13 13:50
voptixjxb26.48 kB07-11-13 13:42
voptiytz0s447.00 B07-11-13 13:50
voptjfi2t32.84 kB07-11-13 13:42
voptjfzfhe371.00 B07-11-13 13:43
voptjgf495411.00 B07-11-13 13:42
voptjygzt31.30 kB07-11-13 13:42
voptk1h7854.75 kB07-11-13 13:42
voptnd9sb21.56 kB07-11-13 13:42
voptne6wt3576.00 B07-11-13 13:42
voptnegw0s3.07 kB07-11-13 13:50
voptq051953.29 kB07-11-13 13:42
voptqz7zs31.42 kB07-11-13 13:42
voptqzkche1.84 kB07-11-13 13:43
voptsxynb23.97 kB07-11-13 13:42
voptsy5s0s1.09 kB07-11-13 13:50
vopttfxvs3968.00 B07-11-13 13:42
vopttyvst33.43 kB07-11-13 13:42
voptxdkjb2722.00 B07-11-13 13:42
voptxevm0s680.00 B07-11-13 13:50
voptxymma211.60 kB07-11-13 13:42
voptyey3ie869.00 B07-11-13 13:43
voptyfer951.79 kB07-11-13 13:42
voptyhhx7568.00 B07-11-13 13:42
_deps4.81 kB07-11-13 13:50
_primary.dat1.09 kB07-11-13 13:50
_primary.dbs3.07 kB07-11-13 13:50
_primary.vhd447.00 B07-11-13 13:50
_primary.dat810.00 B07-11-13 13:50
_primary.dbs955.00 B07-11-13 13:50
_primary.vhd257.00 B07-11-13 13:50
_primary.dat1.42 kB07-11-13 13:50
_primary.dbs2.84 kB07-11-13 13:50
_primary.vhd697.00 B07-11-13 13:50
_primary.dat1.30 kB07-11-13 13:50
_primary.dbs2.77 kB07-11-13 13:50
_primary.vhd362.00 B07-11-13 13:50
_primary.dat1.05 kB07-11-13 13:50
_primary.dbs1.73 kB07-11-13 13:50
_primary.vhd722.00 B07-11-13 13:50
_primary.dat1.79 kB07-11-13 13:50
_primary.dbs3.29 kB07-11-13 13:50
_primary.vhd411.00 B07-11-13 13:50
_primary.dat688.00 B07-11-13 13:50
_primary.dbs1.42 kB07-11-13 13:50
_primary.vhd64.00 B07-11-13 13:50
_primary.dat508.00 B07-11-13 13:50
_primary.dbs1,003.00 B07-11-13 13:50
_primary.vhd64.00 B07-11-13 13:50
_primary.dat485.00 B07-11-13 13:50
_primary.dbs817.00 B07-11-13 13:50
_primary.vhd68.00 B07-11-13 13:50
_primary.dat432.00 B07-11-13 13:50
_primary.dbs826.00 B07-11-13 13:50
_primary.vhd74.00 B07-11-13 13:50
_primary.dat372.00 B07-11-13 13:50
_primary.dbs676.00 B07-11-13 13:50
_primary.vhd80.00 B07-11-13 13:50
_primary.dat494.00 B07-11-13 13:50
_primary.dbs1.01 kB07-11-13 13:50
_primary.vhd80.00 B07-11-13 13:50
_primary.dat869.00 B07-11-13 13:50
_primary.dbs1.84 kB07-11-13 13:50
_primary.vhd371.00 B07-11-13 13:50
_info3.39 kB07-11-13 13:50
_vmake26.00 B07-11-13 13:50
<@_opt>0.00 B07-11-13 13:24
<@_opt1>0.00 B07-11-13 13:17
<@_opt2>0.00 B07-11-13 13:50
<clk_div>0.00 B07-11-13 13:50
<decoder>0.00 B07-11-13 13:50
<display>0.00 B07-11-13 13:50
<encoder>0.00 B07-11-13 13:50
<register>0.00 B07-11-13 13:50
<state_mach>0.00 B07-11-13 13:50
<t1>0.00 B07-11-13 13:50
<t2>0.00 B07-11-13 13:50
<test>0.00 B07-11-13 13:50
<testreg>0.00 B07-11-13 13:50
<te_decoder>0.00 B07-11-13 13:50
<te_encoder>0.00 B07-11-13 13:50
<traffic_ctl>0.00 B07-11-13 13:50
<_temp>0.00 B07-11-13 13:50
<work>0.00 B07-11-13 13:57
<wkt>0.00 B07-11-13 13:57
...
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modelsim.ini (769.16 kB)

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