state_mach.v ( File view )

  • By ketaopku 2013-11-24
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  • Download(s):2
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			module state_mach(
clk_state,
clk_timer,
rest,
state,
numx,
numy);

input clk_state;
input clk_timer;
input rest;
output state;
output numx;
output numy;
reg [3:0]timer_key;//active high  "1"
//reg [5:0]counter;
//reg [5:0]num;
reg [5:0]numx;
reg [5:0]numy;
reg [2:0]state;

always@(posedge clk_timer or negedge rest)
begin
	if(!rest)
		begin
		state<=3'b000;
		timer_key=4'b0001;
		end
	else if(!(numx&&numy))
		begin
			case(state)
			3'b000:begin //numx<=33;
						 //numy<=18;
					     state<=3'b001;
					     timer_key<=4'b0001;//  1
					end	
			3'b001:begin //numx<=15;
						 //numy<=10;
					     state<=3'b010;
					     timer_key<=4'b0010;//  2
					end	
			3'b010:begin //numx<=5;
						 //numy<=3;
					     state<=3'b011;
					     timer_key<=4'b0011;//  3
					end	
			3'b011:begin //numx<=2;
						 //numy<=2;
					     state<=3'b100;
					     timer_key<=4'b0100;//  4
					end	
			3'b100:begin //numx<=18;
						 //numy<=33;
					     state<=3'b101;
					     timer_key<=4'b0101;//  5
					end	
			3'b101:begin //numx<=3;
						 //numy<=15;
					     state<=3'b110;
					     timer_key<=4'b0110;//    6
					end	
			3'b110:begin //numx<=10;
						 //numy<=12;
					     state<=3'b111;
					     timer_key<=4'b0111;//    8
					end	
			3'b111:begin //numx<=2;
						 //numy<=2;
					     state<=3'b000;
					     timer_key<=4'b1000;//   9
					end	
			default:state<=0;
			endcase		 
		end
//	else timer_key<=0;
		
end

//num counter
always@(posedge clk_timer or negedge rest)
if(!rest)
	begin
   numx<=1;
   numy<=1;
   end
else	

	begin
		if((numx&&numy)==0)
			begin
			//timer_key<=1;
			//state<=state+3'b001;
			case(timer_key)
				4'b0001: begin numx<=36;numy<=18;end
				4'b0010: begin numx<=17;numy<=10;end
				4'b0011: begin numx<=6;numy<=3;end
				4'b0100: begin numx<=2;numy<=2;end
				4'b0101: begin numx<=18;numy<=36;end
				4'b0110: begin numx<=3;numy<=17;end
				4'b0111: begin numx<=10;numy<=13;end
				4'b1000: begin numx<=2;numy<=2;end
				default:begin numx<=0;numy<=0;end
			endcase
			end
		else 
			begin
			numx<=numx-1;
			numy<=numy-1;
			end
	end



endmodule 			
...
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Name Size Date
clk_div.v1.40 kB07-11-13 13:49
clk_div.v.bak1.51 kB06-11-13 20:53
decoder.v587.00 B07-11-13 10:40
display.v1.69 kB07-11-13 11:30
display_test.v656.00 B07-11-13 11:11
encoder.v1.04 kB07-11-13 10:30
mac_test.v443.00 B06-11-13 22:32
modelsim.ini50.96 kB07-11-13 13:00
register.v1.02 kB07-11-13 09:05
reg_test.v375.00 B07-11-13 09:05
state_mach.v2.06 kB07-11-13 13:39
state_mach.v.bak2.06 kB07-11-13 13:23
test.v464.00 B07-11-13 13:42
test.v.bak527.00 B07-11-13 11:44
test_decoder.v283.00 B07-11-13 10:44
test_encoder.v433.00 B07-11-13 11:40
tr.cr.mti3.16 kB07-11-13 13:57
tr.mpf59.69 kB07-11-13 13:57
traffic_ctl.v1.26 kB07-11-13 13:43
traffic_ctl.v.bak1.25 kB07-11-13 13:42
vsim.wlf1,008.00 kB07-11-13 13:57
vopt0cca9g64.00 B07-11-13 13:00
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voptmvbj9g5.59 kB07-11-13 13:00
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vopt8k128m411.00 B07-11-13 13:17
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vopttfxvs3968.00 B07-11-13 13:42
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voptxdkjb2722.00 B07-11-13 13:42
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voptxymma211.60 kB07-11-13 13:42
voptyey3ie869.00 B07-11-13 13:43
voptyfer951.79 kB07-11-13 13:42
voptyhhx7568.00 B07-11-13 13:42
_deps4.81 kB07-11-13 13:50
_primary.dat1.09 kB07-11-13 13:50
_primary.dbs3.07 kB07-11-13 13:50
_primary.vhd447.00 B07-11-13 13:50
_primary.dat810.00 B07-11-13 13:50
_primary.dbs955.00 B07-11-13 13:50
_primary.vhd257.00 B07-11-13 13:50
_primary.dat1.42 kB07-11-13 13:50
_primary.dbs2.84 kB07-11-13 13:50
_primary.vhd697.00 B07-11-13 13:50
_primary.dat1.30 kB07-11-13 13:50
_primary.dbs2.77 kB07-11-13 13:50
_primary.vhd362.00 B07-11-13 13:50
_primary.dat1.05 kB07-11-13 13:50
_primary.dbs1.73 kB07-11-13 13:50
_primary.vhd722.00 B07-11-13 13:50
_primary.dat1.79 kB07-11-13 13:50
_primary.dbs3.29 kB07-11-13 13:50
_primary.vhd411.00 B07-11-13 13:50
_primary.dat688.00 B07-11-13 13:50
_primary.dbs1.42 kB07-11-13 13:50
_primary.vhd64.00 B07-11-13 13:50
_primary.dat508.00 B07-11-13 13:50
_primary.dbs1,003.00 B07-11-13 13:50
_primary.vhd64.00 B07-11-13 13:50
_primary.dat485.00 B07-11-13 13:50
_primary.dbs817.00 B07-11-13 13:50
_primary.vhd68.00 B07-11-13 13:50
_primary.dat432.00 B07-11-13 13:50
_primary.dbs826.00 B07-11-13 13:50
_primary.vhd74.00 B07-11-13 13:50
_primary.dat372.00 B07-11-13 13:50
_primary.dbs676.00 B07-11-13 13:50
_primary.vhd80.00 B07-11-13 13:50
_primary.dat494.00 B07-11-13 13:50
_primary.dbs1.01 kB07-11-13 13:50
_primary.vhd80.00 B07-11-13 13:50
_primary.dat869.00 B07-11-13 13:50
_primary.dbs1.84 kB07-11-13 13:50
_primary.vhd371.00 B07-11-13 13:50
_info3.39 kB07-11-13 13:50
_vmake26.00 B07-11-13 13:50
<@_opt>0.00 B07-11-13 13:24
<@_opt1>0.00 B07-11-13 13:17
<@_opt2>0.00 B07-11-13 13:50
<clk_div>0.00 B07-11-13 13:50
<decoder>0.00 B07-11-13 13:50
<display>0.00 B07-11-13 13:50
<encoder>0.00 B07-11-13 13:50
<register>0.00 B07-11-13 13:50
<state_mach>0.00 B07-11-13 13:50
<t1>0.00 B07-11-13 13:50
<t2>0.00 B07-11-13 13:50
<test>0.00 B07-11-13 13:50
<testreg>0.00 B07-11-13 13:50
<te_decoder>0.00 B07-11-13 13:50
<te_encoder>0.00 B07-11-13 13:50
<traffic_ctl>0.00 B07-11-13 13:50
<_temp>0.00 B07-11-13 13:50
<work>0.00 B07-11-13 13:57
<wkt>0.00 B07-11-13 13:57
...
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state_mach.v (769.16 kB)

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