test.v ( File view )

  • By ketaopku 2013-11-24
  • View(s):33
  • Download(s):2
  • Point(s): 1
			`timescale 1ns/1ns
module test;
reg clk;
reg rest;
//output sd0;
//output sd1;
/*output [7:0]dataxh;
output [7:0]dataxl;
output [7:0]datayh;
output [7:0]datayl;*/
wire [7:0]  data;
wire [15:0] led;
wire [7:0]  wl;

 
 initial
 begin
     clk=0;
     rest=0;
     #100 rest=1;
     #100 rest=0;
     #100 rest=1;
 end


always #20 clk=~clk;

traffic_ctl a(
.clk(clk),
.rest(rest),
.wl(wl),
.data(data),
//dataxh,
//dataxl,
//datayh,
//datayl,
.led(led));
endmodule 			
...
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Name Size Date
clk_div.v1.40 kB07-11-13 13:49
clk_div.v.bak1.51 kB06-11-13 20:53
decoder.v587.00 B07-11-13 10:40
display.v1.69 kB07-11-13 11:30
display_test.v656.00 B07-11-13 11:11
encoder.v1.04 kB07-11-13 10:30
mac_test.v443.00 B06-11-13 22:32
modelsim.ini50.96 kB07-11-13 13:00
register.v1.02 kB07-11-13 09:05
reg_test.v375.00 B07-11-13 09:05
state_mach.v2.06 kB07-11-13 13:39
state_mach.v.bak2.06 kB07-11-13 13:23
test.v464.00 B07-11-13 13:42
test.v.bak527.00 B07-11-13 11:44
test_decoder.v283.00 B07-11-13 10:44
test_encoder.v433.00 B07-11-13 11:40
tr.cr.mti3.16 kB07-11-13 13:57
tr.mpf59.69 kB07-11-13 13:57
traffic_ctl.v1.26 kB07-11-13 13:43
traffic_ctl.v.bak1.25 kB07-11-13 13:42
vsim.wlf1,008.00 kB07-11-13 13:57
vopt0cca9g64.00 B07-11-13 13:00
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<@_opt>0.00 B07-11-13 13:24
<@_opt1>0.00 B07-11-13 13:17
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<clk_div>0.00 B07-11-13 13:50
<decoder>0.00 B07-11-13 13:50
<display>0.00 B07-11-13 13:50
<encoder>0.00 B07-11-13 13:50
<register>0.00 B07-11-13 13:50
<state_mach>0.00 B07-11-13 13:50
<t1>0.00 B07-11-13 13:50
<t2>0.00 B07-11-13 13:50
<test>0.00 B07-11-13 13:50
<testreg>0.00 B07-11-13 13:50
<te_decoder>0.00 B07-11-13 13:50
<te_encoder>0.00 B07-11-13 13:50
<traffic_ctl>0.00 B07-11-13 13:50
<_temp>0.00 B07-11-13 13:50
<work>0.00 B07-11-13 13:57
<wkt>0.00 B07-11-13 13:57
...
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test.v (769.16 kB)

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