usb_dcd_int.c ( File view )

  • By gregkam 2014-10-06
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			/**
  ******************************************************************************
  * @file    usb_dcd_int.c
  * @author  MCD Application Team
  * @version V2.1.0
  * @date    19-March-2012
  * @brief   Peripheral Device interrupt subroutines
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
  *
  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  * You may not use this file except in compliance with the License.
  * You may obtain a copy of the License at:
  *
  *        http://www.st.com/software_license_agreement_liberty_v2
  *
  * Unless required by applicable law or agreed to in writing, software 
  * distributed under the License is distributed on an "AS IS" BASIS, 
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "usb_dcd_int.h"
/** @addtogroup USB_OTG_DRIVER
* @{

*/

/** @defgroup USB_DCD_INT 
* @brief This file contains the interrupt subroutines for the Device mode.
* @{

*/


/** @defgroup USB_DCD_INT_Private_Defines
* @{

*/ 
/**
* @
}
*/ 


/** @defgroup USB_DCD_INT_Private_TypesDefinitions
* @{

*/ 
/**
* @
}
*/ 



/** @defgroup USB_DCD_INT_Private_Macros
* @{

*/ 
/**
* @
}
*/ 


/** @defgroup USB_DCD_INT_Private_Variables
* @{

*/ 
/**
* @
}
*/ 


/** @defgroup USB_DCD_INT_Private_FunctionPrototypes
* @{

*/ 
/* static functions */
static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum);

/* Interrupt Handlers */
static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev);
static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev);
static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev);

static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev);
static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev , uint32_t epnum);

static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev);
static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev);
static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev);
static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev);

static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev);
static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev);
#ifdef VBUS_SENSING_ENABLED
static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev);
static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev);
#endif

/**
* @
}
*/ 


/** @defgroup USB_DCD_INT_Private_Functions
* @{

*/ 


#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED  
/**
* @brief  USBD_OTG_EP1OUT_ISR_Handler
*         handles all USB Interrupts
* @param  pdev: device instance
* @retval status
*/
uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
{

  
  USB_OTG_DOEPINTn_TypeDef  doepint;
  USB_OTG_DEPXFRSIZ_TypeDef  deptsiz;  
  
  doepint.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[1]->DOEPINT);
  doepint.d32&= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOUTEP1MSK);
  
  /* Transfer complete */
  if ( doepint.b.xfercompl )
  {

    /* Clear the bit in DOEPINTn for this interrupt */
    CLEAR_OUT_EP_INTR(1, xfercompl);
    if (pdev->cfg.dma_enable == 1)
    {

      deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[1]->DOEPTSIZ));
      /*ToDo : handle more than one single MPS size packet */
      pdev->dev.out_ep[1].xfer_count = pdev->dev.out_ep[1].maxpacket - \
        deptsiz.b.xfersize;
    
}    
    /* Inform upper layer: data ready */
    /* RX COMPLETE */
    USBD_DCD_INT_fops->DataOutStage(pdev , 1);
    
  
}
  
  /* Endpoint disable  */
  if ( doepint.b.epdisabled )
  {

    /* Clear the bit in DOEPINTn for this interrupt */
    CLEAR_OUT_EP_INTR(1, epdisabled);
  
}

  return 1;

}

/**
* @brief  USBD_OTG_EP1IN_ISR_Handler
*         handles all USB Interrupts
* @param  pdev: device instance
* @retval status
*/
uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
{

  
  USB_OTG_DIEPINTn_TypeDef  diepint;
  uint32_t fifoemptymsk, msk, emp;
  
  msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DINEP1MSK);
  emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK);
  msk |= ((emp >> 1 ) & 0x1) << 7;
  diepint.d32  = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[1]->DIEPINT) & msk;  
  
  if ( diepint.b.xfercompl )
  {

    fifoemptymsk = 0x1 << 1;
    USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0);
    CLEAR_IN_EP_INTR(1, xfercompl);
    /* TX COMPLETE */
    USBD_DCD_INT_fops->DataInStage(pdev , 1);
  
}
  if ( diepint.b.epdisabled )
  {

    CLEAR_IN_EP_INTR(1, epdisabled);
  
}  
  if ( diepint.b.timeout )
  {

    CLEAR_IN_EP_INTR(1, timeout);
  
}
  if (diepint.b.intktxfemp)
  {

    CLEAR_IN_EP_INTR(1, intktxfemp);
  
}
  if (diepint.b.inepnakeff)
  {

    CLEAR_IN_EP_INTR(1, inepnakeff);
  
}
  if (diepint.b.emptyintr)
  {

    DCD_WriteEmptyTxFifo(pdev , 1);
    CLEAR_IN_EP_INTR(1, emptyintr);
  
}
  return 1;

}
#endif

/**
* @brief  STM32_USBF_OTG_ISR_Handler
*         handles all USB Interrupts
* @param  pdev: device instance
* @retval status
*/
uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
{

  USB_OTG_GINTSTS_TypeDef  gintr_status;
  uint32_t retval = 0;
  
  if (USB_OTG_IsDeviceMode(pdev)) /* ensure that we are in device mode */
  {

    gintr_status.d32 = USB_OTG_ReadCoreItr(pdev);
    if (!gintr_status.d32) /* avoid spurious interrupt */
    {

      return 0;
    
}
    
    if (gintr_status.b.outepintr)
    {

      retval |= DCD_HandleOutEP_ISR(pdev);
    
}    
    
    if (gintr_status.b.inepint)
    {

      retval |= DCD_HandleInEP_ISR(pdev);
    
}
    
    if (gintr_status.b.modemismatch)
    {

      USB_OTG_GINTSTS_TypeDef  gintsts;
      
      /* Clear interrupt */
      gintsts.d32 = 0;
      gintsts.b.modemismatch = 1;
      USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
    
}
    
    if (gintr_status.b.wkupintr)
    {

      retval |= DCD_HandleResume_ISR(pdev);
    
}
    
    if (gintr_status.b.usbsuspend)
    {

      retval |= DCD_HandleUSBSuspend_ISR(pdev);
    
}
    if (gintr_status.b.sofintr)
    {

      retval |= DCD_HandleSof_ISR(pdev);
      
    
}
    
    if (gintr_status.b.rxstsqlvl)
    {

      retval |= DCD_HandleRxStatusQueueLevel_ISR(pdev);
      
    
}
    
    if (gintr_status.b.usbreset)
    {

      retval |= DCD_HandleUsbReset_ISR(pdev);
      
    
}
    if (gintr_status.b.enumdone)
    {

      retval |= DCD_HandleEnumDone_ISR(pdev);
    
}
    
    if (gintr_status.b.incomplisoin)
    {

      retval |= DCD_IsoINIncomplete_ISR(pdev);
    
}

    if (gintr_status.b.incomplisoout)
    {

      retval |= DCD_IsoOUTIncomplete_ISR(pdev);
    
}    
#ifdef VBUS_SENSING_ENABLED
    if (gintr_status.b.sessreqintr)
    {

      retval |= DCD_SessionRequest_ISR(pdev);
    
}

    if (gintr_status.b.otgintr)
    {

      retval |= DCD_OTG_ISR(pdev);
    
}   
#endif    
  
}
  return retval;

}

#ifdef VBUS_SENSING_ENABLED
/**
* @brief  DCD_SessionRequest_ISR
*         Indicates that the USB_OTG controller has detected a connection
* @param  pdev: device instance
* @retval status
*/
static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev)
{

  USB_OTG_GINTSTS_TypeDef  gintsts;  
  USBD_DCD_INT_fops->DevConnected (pdev);

  /* Clear interrupt */
  gintsts.d32 = 0;
  gintsts.b.sessreqintr = 1;
  USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);   
  return 1;

}

/**
* @brief  DCD_OTG_ISR
*         Indicates that the USB_OTG controller has detected an OTG event:
*                 used to detect the end of session i.e. disconnection
* @param  pdev: device instance
* @retval status
*/
static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev)
{


  USB_OTG_GOTGINT_TypeDef  gotgint;

  gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT);
  
  if (gotgint.b.sesenddet)
  {

    USBD_DCD_INT_fops->DevDisconnected (pdev);
  
}
  /* Clear OTG interrupt */
  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32); 
  return 1;

}
#endif
/**
* @brief  DCD_HandleResume_ISR
*         Indicates that the USB_OTG controller has detected a resume or
*                 remote Wake-up sequence
* @param  pdev: device instance
* @retval status
*/
static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev)
{

  USB_OTG_GINTSTS_TypeDef  gintsts;
  USB_OTG_DCTL_TypeDef     devctl;
  USB_OTG_PCGCCTL_TypeDef  power;
  
  if(pdev->cfg.low_power)
  {

    /* un-gate USB Core clock */
    power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL);
    power.b.gatehclk = 0;
    power.b.stoppclk = 0;
    USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
  
}
  
  /* Clear the Remote Wake-up Signaling */
  devctl.d32 = 0;
  devctl.b.rmtwkupsig = 1;
  USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, devctl.d32, 0);
  
  /* Inform upper layer by the Resume Event */
  USBD_DCD_INT_fops->Resume (pdev);
  
  /* Clear interrupt */
  gintsts.d32 = 0;
  gintsts.b.wkupintr = 1;
  USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
  return 1;

}

/**
* @brief  USB_OTG_HandleUSBSuspend_ISR
*         Indicates that SUSPEND state has been detected on the USB
* @param  pdev: device instance
* @retval status
*/
static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev)
{

  USB_OTG_GINTSTS_TypeDef  gintsts;
  USB_OTG_PCGCCTL_TypeDef  power;
  USB_OTG_DSTS_TypeDef     dsts;
  __IO uint8_t prev_status = 0;
  
  prev_status = pdev->dev.device_status;
  USBD_DCD_INT_fops->Suspend (pdev);      
  
  dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
    
  /* Clear interrupt */
  gintsts.d32 = 0;
  gintsts.b.usbsuspend = 1;
  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
  
  if((pdev->cfg.low_power) && (dsts.b.suspsts == 1)  && 
    (pdev->dev.connection_status == 1) && 
    (prev_status  == USB_OTG_CONFIGURED))
  {

	/*  switch-off the clocks */
    power.d32 = 0;
    power.b.stoppclk = 1;
    USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32);  
    
    power.b.gatehclk = 1;
    USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, p
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usb_dcd.h4.48 kB2013-04-23|01:09
usb_dcd_int.h3.03 kB2013-04-23|01:09
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usb_hcd_int.h3.65 kB2013-04-23|01:09
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usb_regs.h21.22 kB2013-04-23|01:09
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