core_cm4.h ( File view )

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 * @file     core_cm4.h
 * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
 * @version  V2.10
 * @date     19. July 2011
 * @note
 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
 * @par
 * ARM Limited (ARM) is supplying this software for use with Cortex-M
 * processor based microcontrollers.  This file can be freely distributed
 * within development tools that are supporting such ARM based processors.
 * @par
#if defined ( __ICCARM__ )
 #pragma system_include  /* treat file as system include file for MISRA check */

#ifdef __cplusplus
 extern "C" {


#ifndef __CORE_CM4_H_GENERIC
#define __CORE_CM4_H_GENERIC

/** \mainpage CMSIS Cortex-M4

  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
  It consists of:

     - Cortex-M Core Register Definitions
     - Cortex-M functions
     - Cortex-M instructions
     - Cortex-M SIMD instructions

  The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease
  access to the Cortex-M Core

/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
  CMSIS violates following MISRA-C2004 Rules:
   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
     Function definitions in header files are used to allow 'inlining'. 

   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{
     Unions are used for effective representation of core registers.
   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
     Function-like macros are used to allow more efficient code. 


 *                 CMSIS definitions
/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
  This file defines all structures and symbols for CMSIS core:
   - CMSIS version number
   - Cortex-M core
   - Cortex-M core Revision Number


/*  CMSIS CM4 definitions */
#define __CM4_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
#define __CM4_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */

#define __CORTEX_M                (0x04)                                                       /*!< Cortex core                    */

#if   defined ( __CC_ARM )
  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

#elif defined ( __ICCARM__ )
  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

#elif defined ( __GNUC__ )
  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

#elif defined ( __TASKING__ )
  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */


/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
#if defined ( __CC_ARM )
  #if defined __TARGET_FPU_VFP
    #if (__FPU_PRESENT == 1)
      #define __FPU_USED       1
      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
      #define __FPU_USED       0
    #define __FPU_USED         0

#elif defined ( __ICCARM__ )
  #if defined __ARMVFP__
    #if (__FPU_PRESENT == 1)
      #define __FPU_USED       1
      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
      #define __FPU_USED       0
    #define __FPU_USED         0

#elif defined ( __GNUC__ )
  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
    #if (__FPU_PRESENT == 1)
      #define __FPU_USED       1
      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
      #define __FPU_USED       0
    #define __FPU_USED         0

#elif defined ( __TASKING__ )
    /* add preprocessor checks to define __FPU_USED */
    #define __FPU_USED         0

#include <stdint.h>                      /*!< standard types definitions                      */
#include <core_cmInstr.h>                /*!< Core Instruction Access                         */
#include <core_cmFunc.h>                 /*!< Core Function Access                            */
#include <core_cm4_simd.h>               /*!< Compiler specific SIMD Intrinsics               */

#endif /* __CORE_CM4_H_GENERIC */



/* check device defines and use defaults */
  #ifndef __CM4_REV
    #define __CM4_REV               0x0000
    #warning "__CM4_REV not defined in device header file; using default!"

  #ifndef __FPU_PRESENT
    #define __FPU_PRESENT             0
    #warning "__FPU_PRESENT not defined in device header file; using default!"

  #ifndef __MPU_PRESENT
    #define __MPU_PRESENT             0
    #warning "__MPU_PRESENT not defined in device header file; using default!"

  #ifndef __NVIC_PRIO_BITS
    #define __NVIC_PRIO_BITS          4
    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

  #ifndef __Vendor_SysTickConfig
    #define __Vendor_SysTickConfig    0
    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

/* IO definitions (access restrictions to peripheral registers) */
#ifdef __cplusplus
  #define   __I     volatile             /*!< defines 'read only' permissions                 */
  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
#define     __O     volatile             /*!< defines 'write only' permissions                */
#define     __IO    volatile             /*!< defines 'read / write' permissions              */

} end of group CMSIS_core_definitions */

 *                 Register Abstraction
/** \defgroup CMSIS_core_register CMSIS Core Register
  Core Register contain:
  - Core Register
  - Core NVIC Register
  - Core SCB Register
  - Core SysTick Register
  - Core Debug Register
  - Core MPU Register
  - Core FPU Register

/** \ingroup  CMSIS_core_register
    \defgroup CMSIS_CORE CMSIS Core
  Type definitions for the Cortex-M Core Registers


/** \brief  Union type to access the Application Program Status Register (APSR).
typedef union


#if (__CORTEX_M != 0x04)
    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
} b;                                   /*!< Structure used for bit  access                  */
  uint32_t w;                            /*!< Type      used for word access                  */

} APSR_Type;

/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
typedef union


    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
} b;                                   /*!< Structure used for bit  access                  */
  uint32_t w;                            /*!< Type      used for word access                  */

} IPSR_Type;

/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
typedef union


    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
#if (__CORTEX_M != 0x04)
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spi3.o479.34 kB2014-09-30|11:22
startup_stm32f4xx.d59.00 B2014-09-30|11:21
startup_stm32f4xx.o7.73 kB2014-09-30|11:21
stm32adc.crf416.63 kB2014-09-30|11:21
stm32adc.d1.84 kB2014-09-30|11:21
stm32adc.o444.02 kB2014-09-30|11:21
stm32f4xx_adc.crf422.59 kB2014-09-30|11:21
stm32f4xx_adc.d2.01 kB2014-09-30|11:21
stm32f4xx_adc.o487.58 kB2014-09-30|11:21
stm32f4xx_dbgmcu.crf415.63 kB2014-09-30|11:21
stm32f4xx_dbgmcu.d2.12 kB2014-09-30|11:21
stm32f4xx_dbgmcu.o440.03 kB2014-09-30|11:21
stm32f4xx_dcmi.crf417.75 kB2014-09-30|11:21
stm32f4xx_dcmi.d2.04 kB2014-09-30|11:21
stm32f4xx_dcmi.o453.16 kB2014-09-30|11:21
stm32f4xx_dma.crf422.48 kB2014-09-30|11:21
stm32f4xx_dma.d2.01 kB2014-09-30|11:21
stm32f4xx_dma.o461.39 kB2014-09-30|11:21
stm32f4xx_exti.crf416.59 kB2014-09-30|11:21
stm32f4xx_exti.d2.04 kB2014-09-30|11:21
stm32f4xx_exti.o444.07 kB2014-09-30|11:21
stm32f4xx_flash.crf420.54 kB2014-09-30|11:21
stm32f4xx_flash.d2.08 kB2014-09-30|11:21
stm32f4xx_flash.o475.34 kB2014-09-30|11:21
stm32f4xx_gpio.crf417.89 kB2014-09-30|11:21
stm32f4xx_gpio.d2.04 kB2014-09-30|11:21
stm32f4xx_gpio.o453.07 kB2014-09-30|11:21
stm32f4xx_it.crf415.49 kB2014-09-30|11:21
stm32f4xx_it.d1.97 kB2014-09-30|11:21
stm32f4xx_it.o444.81 kB2014-09-30|11:21
stm32f4xx_pwr.crf417.44 kB2014-09-30|11:21
stm32f4xx_pwr.d2.01 kB2014-09-30|11:21
stm32f4xx_pwr.o449.88 kB2014-09-30|11:21
stm32f4xx_rcc.crf424.55 kB2014-09-30|11:21
stm32f4xx_rcc.d2.01 kB2014-09-30|11:21
stm32f4xx_rcc.o495.22 kB2014-09-30|11:21
stm32f4xx_rng.crf415.92 kB2014-09-30|11:21
stm32f4xx_rng.d2.01 kB2014-09-30|11:21
stm32f4xx_rng.o443.76 kB2014-09-30|11:21
stm32f4xx_rtc.crf433.11 kB2014-09-30|11:21
stm32f4xx_rtc.d2.01 kB2014-09-30|11:21
stm32f4xx_rtc.o516.53 kB2014-09-30|11:21
stm32f4xx_sdio.crf419.94 kB2014-09-30|11:21
stm32f4xx_sdio.d2.04 kB2014-09-30|11:21
stm32f4xx_sdio.o474.00 kB2014-09-30|11:21
stm32f4xx_spi.crf420.43 kB2014-09-30|11:21
stm32f4xx_spi.d2.01 kB2014-09-30|11:21
stm32f4xx_spi.o468.64 kB2014-09-30|11:21
stm32f4xx_syscfg.crf416.09 kB2014-09-30|11:21
stm32f4xx_syscfg.d2.12 kB2014-09-30|11:21
stm32f4xx_syscfg.o441.90 kB2014-09-30|11:21
stm32f4xx_tim.crf435.53 kB2014-09-30|11:21
stm32f4xx_tim.d2.01 kB2014-09-30|11:21
stm32f4xx_tim.o563.30 kB2014-09-30|11:21
stm32f4xx_usart.crf420.95 kB2014-09-30|11:21
stm32f4xx_usart.d2.08 kB2014-09-30|11:21
stm32f4xx_usart.o474.46 kB2014-09-30|11:21
stm32f4xx_wwdg.crf416.16 kB2014-09-30|11:21
stm32f4xx_wwdg.d2.04 kB2014-09-30|11:21
stm32f4xx_wwdg.o443.88 kB2014-09-30|11:21
system_stm32f4xx.crf417.16 kB2014-09-30|11:21
system_stm32f4xx.d2.06 kB2014-09-30|11:21
system_stm32f4xx.o438.50 kB2014-09-30|11:21
uart1.crf455.77 kB2014-09-30|11:22
uart1.d2.97 kB2014-09-30|11:22
uart1.o490.19 kB2014-09-30|11:22
ultrasonic.crf420.98 kB2014-09-30|11:22
ultrasonic.d2.09 kB2014-09-30|11:22
ultrasonic.o451.47 kB2014-09-30|11:22
usart1dmatx.crf418.27 kB2014-09-30|11:22
usart1dmatx.d2.02 kB2014-09-30|11:22
usart1dmatx.o444.86 kB2014-09-30|11:22
Protel76.01 kB2013-11-26|21:29
01.97 kB
startup_stm32f4xx.s28.82 kB2011-10-28|10:31
system_stm32f4xx.c21.36 kB2013-06-17|19:09
system_stm32f4xx.h2.05 kB2011-10-28|10:31
startup_stm32f4xx.lst73.83 kB2014-09-30|11:21
01.97 kB
main.c9.82 kB2014-02-27|11:56
main.h1.86 kB2012-11-15|11:46
Read_Me.txt6.96 kB2013-12-16|21:46
stm32f4xx_conf.h3.71 kB2013-03-05|14:42
stm32f4xx_it.c4.34 kB2013-03-05|12:05
stm32f4xx_it.h2.00 kB2013-03-05|12:06
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core_cm4.h (12.86 MB)

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