stm32f4xx_cryp.c ( File view )

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			/**
  ******************************************************************************
  * @file    stm32f4xx_cryp.c
  * @author  MCD Application Team
  * @version V1.0.0
  * @date    30-September-2011
  * @brief   This file provides firmware functions to manage the following 
  *          functionalities of the  Cryptographic processor (CRYP) peripheral:           
  *           - Initialization and Configuration functions
  *           - Data treatment functions 
  *           - Context swapping functions     
  *           - DMA interface function       
  *           - Interrupts and flags management       
  *
  *  @verbatim
  *                               
  *          ===================================================================      
  *                                 How to use this driver
  *          =================================================================== 
  *          1. Enable the CRYP controller clock using 
  *              RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
  *
  *          2. Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if 
  *             needed CRYP_IVInit(). 
  *
  *          3. Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function.
  *
  *          4. Enable the CRYP controller using the CRYP_Cmd() function. 
  *
  *          5. If using DMA for Data input and output transfer, 
  *             Activate the needed DMA Requests using CRYP_DMACmd() function 
  
  *          6. If DMA is not used for data transfer, use CRYP_DataIn() and 
  *             CRYP_DataOut() functions to enter data to IN FIFO and get result
  *             from OUT FIFO.
  *
  *          7. To control CRYP events you can use one of the following 
  *              two methods:
  *               - Check on CRYP flags using the CRYP_GetFlagStatus() function.  
  *               - Use CRYP interrupts through the function CRYP_ITConfig() at 
  *                 initialization phase and CRYP_GetITStatus() function into 
  *                 interrupt routines in processing phase.
  *       
  *          8. Save and restore Cryptographic processor context using  
  *             CRYP_SaveContext() and CRYP_RestoreContext() functions.     
  *
  *
  *          ===================================================================  
  *                Procedure to perform an encryption or a decryption
  *          ===================================================================  
  *
  *      Initialization
  *      ===============  
  *     1. Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and 
  *        CRYP_IVInit functions:
  *        - Configure the key size (128-, 192- or 256-bit, in the AES only) 
  *        - Enter the symmetric key 
  *        - Configure the data type
  *        - In case of decryption in AES-ECB or AES-CBC, you must prepare 
  *          the key: configure the key preparation mode. Then Enable the CRYP 
  *          peripheral using CRYP_Cmd() function: the BUSY flag is set. 
  *          Wait until BUSY flag is reset : the key is prepared for decryption
  *       - Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the 
  *          AES in ECB/CBC/CTR) 
  *       - Configure the direction (encryption/decryption).
  *       - Write the initialization vectors (in CBC or CTR modes only)
  *
  *    2. Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function
  *
  *
  *    Basic Processing mode (polling mode) 
  *    ====================================  
  *    1. Enable the cryptographic processor using CRYP_Cmd() function.
  *
  *    2. Write the first blocks in the input FIFO (2 to 8 words) using 
  *       CRYP_DataIn() function.
  *
  *    3. Repeat the following sequence until the complete message has been 
  *       processed:
  *
  *       a) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() 
  *          function), then read the OUT-FIFO using CRYP_DataOut() function
  *          (1 block or until the FIFO is empty)
  *
  *       b) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() 
  *          function then write the IN FIFO using CRYP_DataIn() function 
  *          (1 block or until the FIFO is full)
  *
  *    4. At the end of the processing, CRYP_FLAG_BUSY flag will be reset and 
  *        both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is 
  *        reset). You can disable the peripheral using CRYP_Cmd() function.
  *
  *    Interrupts Processing mode 
  *    ===========================
  *    In this mode, Processing is done when the data are transferred by the 
  *    CPU during interrupts.
  *
  *    1. Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using 
  *       CRYP_ITConfig() function.
  *
  *    2. Enable the cryptographic processor using CRYP_Cmd() function.
  *
  *    3. In the CRYP_IT_INI interrupt handler : load the input message into the 
  *       IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a 
  *       time, or load data until the IN FIFO is full. When the last word of
  *       the message has been entered into the IN FIFO, disable the CRYP_IT_INI 
  *       interrupt (using CRYP_ITConfig() function).
  *
  *    4. In the CRYP_IT_OUTI interrupt handler : read the output message from 
  *       the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or 
  *       4 words) at a time or read data until the FIFO is empty.
  *       When the last word has been read, INIM=0, BUSY=0 and both FIFOs are 
  *       empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). 
  *       You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() 
  *       function) and you can disable the peripheral using CRYP_Cmd() function.
  *
  *    DMA Processing mode 
  *    ====================
  *    In this mode, Processing is done when the DMA is used to transfer the 
  *    data from/to the memory.
  *
  *    1. Configure the DMA controller to transfer the input data from the 
  *       memory using DMA_Init() function. 
  *       The transfer length is the length of the message. 
  *       As message padding is not managed by the peripheral, the message 
  *       length must be an entire number of blocks. The data are transferred 
  *       in burst mode. The burst length is 4 words in the AES and 2 or 4 
  *       words in the DES/TDES. The DMA should be configured to set an 
  *       interrupt on transfer completion of the output data to indicate that 
  *       the processing is finished. 
  *       Refer to DMA peripheral driver for more details.  
  *
  *    2. Enable the cryptographic processor using CRYP_Cmd() function. 
  *       Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT 
  *       using CRYP_DMACmd() function.
  *
  *    3. All the transfers and processing are managed by the DMA and the 
  *       cryptographic processor. The DMA transfer complete interrupt indicates 
  *       that the processing is complete. Both FIFOs are normally empty and 
  *       CRYP_FLAG_BUSY flag is reset.
  *
  *  @endverbatim
  *
  ******************************************************************************
  * @attention
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
  ******************************************************************************  
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_rcc.h"

/** @addtogroup STM32F4xx_StdPeriph_Driver
  * @{

  */

/** @defgroup CRYP 
  * @brief CRYP driver modules
  * @{

  */ 

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define FLAG_MASK     ((uint8_t)0x20)
#define MAX_TIMEOUT   ((uint16_t)0xFFFF)

/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/

/** @defgroup CRYP_Private_Functions
  * @{

  */ 

/** @defgroup CRYP_Group1 Initialization and Configuration functions
 *  @brief    Initialization and Configuration functions 
 *
@verbatim    
 ===============================================================================
                      Initialization and Configuration functions
 ===============================================================================  
  This section provides functions allowing to 
   - Initialize the cryptographic Processor using CRYP_Init() function 
      -  Encrypt or Decrypt 
      -  mode : TDES-ECB, TDES-CBC, 
                DES-ECB, DES-CBC, 
                AES-ECB, AES-CBC, AES-CTR, AES-Key 
      - DataType :  32-bit data, 16-bit data, bit data or bit-string
      - Key Size (only in AES modes)
   - Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function 
   - Configure the Initialization Vectors(IV) for CBC and CTR modes using 
     CRYP_IVInit() function.  
   - Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function.                         
   - Enable or disable the CRYP Processor using CRYP_Cmd() function 
    
   
@endverbatim
  * @{

  */
/**
  * @brief  Deinitializes the CRYP peripheral registers to their default reset values
  * @param  None
  * @retval None
  */
void CRYP_DeInit(void)
{

  /* Enable CRYP reset state */
  RCC_AHB2
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osqmem.d1.82 kB2014-09-30|11:22
osqmem.o443.41 kB2014-09-30|11:22
pid.crf3.46 kB2014-09-30|11:22
pid.d84.00 B2014-09-30|11:22
pid.o24.76 kB2014-09-30|11:22
pwm_input.crf420.54 kB2014-09-30|11:21
pwm_input.d1.99 kB2014-09-30|11:21
pwm_input.o453.93 kB2014-09-30|11:21
pwm_output.crf458.55 kB2014-09-30|11:22
pwm_output.d3.32 kB2014-09-30|11:22
pwm_output.o490.34 kB2014-09-30|11:22
quadrotor.crf458.90 kB2014-09-30|11:22
quadrotor.d3.26 kB2014-09-30|11:22
quadrotor.o502.92 kB2014-09-30|11:22
sd_init.crf421.82 kB2014-09-30|11:22
sd_init.d1.83 kB2014-09-30|11:22
sd_init.o464.06 kB2014-09-30|11:22
spi3.crf452.77 kB2014-09-30|11:22
spi3.d2.79 kB2014-09-30|11:22
spi3.o479.34 kB2014-09-30|11:22
startup_stm32f4xx.d59.00 B2014-09-30|11:21
startup_stm32f4xx.o7.73 kB2014-09-30|11:21
stm32adc.crf416.63 kB2014-09-30|11:21
stm32adc.d1.84 kB2014-09-30|11:21
stm32adc.o444.02 kB2014-09-30|11:21
stm32f4xx_adc.crf422.59 kB2014-09-30|11:21
stm32f4xx_adc.d2.01 kB2014-09-30|11:21
stm32f4xx_adc.o487.58 kB2014-09-30|11:21
stm32f4xx_dbgmcu.crf415.63 kB2014-09-30|11:21
stm32f4xx_dbgmcu.d2.12 kB2014-09-30|11:21
stm32f4xx_dbgmcu.o440.03 kB2014-09-30|11:21
stm32f4xx_dcmi.crf417.75 kB2014-09-30|11:21
stm32f4xx_dcmi.d2.04 kB2014-09-30|11:21
stm32f4xx_dcmi.o453.16 kB2014-09-30|11:21
stm32f4xx_dma.crf422.48 kB2014-09-30|11:21
stm32f4xx_dma.d2.01 kB2014-09-30|11:21
stm32f4xx_dma.o461.39 kB2014-09-30|11:21
stm32f4xx_exti.crf416.59 kB2014-09-30|11:21
stm32f4xx_exti.d2.04 kB2014-09-30|11:21
stm32f4xx_exti.o444.07 kB2014-09-30|11:21
stm32f4xx_flash.crf420.54 kB2014-09-30|11:21
stm32f4xx_flash.d2.08 kB2014-09-30|11:21
stm32f4xx_flash.o475.34 kB2014-09-30|11:21
stm32f4xx_gpio.crf417.89 kB2014-09-30|11:21
stm32f4xx_gpio.d2.04 kB2014-09-30|11:21
stm32f4xx_gpio.o453.07 kB2014-09-30|11:21
stm32f4xx_it.crf415.49 kB2014-09-30|11:21
stm32f4xx_it.d1.97 kB2014-09-30|11:21
stm32f4xx_it.o444.81 kB2014-09-30|11:21
stm32f4xx_pwr.crf417.44 kB2014-09-30|11:21
stm32f4xx_pwr.d2.01 kB2014-09-30|11:21
stm32f4xx_pwr.o449.88 kB2014-09-30|11:21
stm32f4xx_rcc.crf424.55 kB2014-09-30|11:21
stm32f4xx_rcc.d2.01 kB2014-09-30|11:21
stm32f4xx_rcc.o495.22 kB2014-09-30|11:21
stm32f4xx_rng.crf415.92 kB2014-09-30|11:21
stm32f4xx_rng.d2.01 kB2014-09-30|11:21
stm32f4xx_rng.o443.76 kB2014-09-30|11:21
stm32f4xx_rtc.crf433.11 kB2014-09-30|11:21
stm32f4xx_rtc.d2.01 kB2014-09-30|11:21
stm32f4xx_rtc.o516.53 kB2014-09-30|11:21
stm32f4xx_sdio.crf419.94 kB2014-09-30|11:21
stm32f4xx_sdio.d2.04 kB2014-09-30|11:21
stm32f4xx_sdio.o474.00 kB2014-09-30|11:21
stm32f4xx_spi.crf420.43 kB2014-09-30|11:21
stm32f4xx_spi.d2.01 kB2014-09-30|11:21
stm32f4xx_spi.o468.64 kB2014-09-30|11:21
stm32f4xx_syscfg.crf416.09 kB2014-09-30|11:21
stm32f4xx_syscfg.d2.12 kB2014-09-30|11:21
stm32f4xx_syscfg.o441.90 kB2014-09-30|11:21
stm32f4xx_tim.crf435.53 kB2014-09-30|11:21
stm32f4xx_tim.d2.01 kB2014-09-30|11:21
stm32f4xx_tim.o563.30 kB2014-09-30|11:21
stm32f4xx_usart.crf420.95 kB2014-09-30|11:21
stm32f4xx_usart.d2.08 kB2014-09-30|11:21
stm32f4xx_usart.o474.46 kB2014-09-30|11:21
stm32f4xx_wwdg.crf416.16 kB2014-09-30|11:21
stm32f4xx_wwdg.d2.04 kB2014-09-30|11:21
stm32f4xx_wwdg.o443.88 kB2014-09-30|11:21
system_stm32f4xx.crf417.16 kB2014-09-30|11:21
system_stm32f4xx.d2.06 kB2014-09-30|11:21
system_stm32f4xx.o438.50 kB2014-09-30|11:21
uart1.crf455.77 kB2014-09-30|11:22
uart1.d2.97 kB2014-09-30|11:22
uart1.o490.19 kB2014-09-30|11:22
ultrasonic.crf420.98 kB2014-09-30|11:22
ultrasonic.d2.09 kB2014-09-30|11:22
ultrasonic.o451.47 kB2014-09-30|11:22
usart1dmatx.crf418.27 kB2014-09-30|11:22
usart1dmatx.d2.02 kB2014-09-30|11:22
usart1dmatx.o444.86 kB2014-09-30|11:22
Protel76.01 kB2013-11-26|21:29
01.97 kB
startup_stm32f4xx.s28.82 kB2011-10-28|10:31
system_stm32f4xx.c21.36 kB2013-06-17|19:09
system_stm32f4xx.h2.05 kB2011-10-28|10:31
startup_stm32f4xx.lst73.83 kB2014-09-30|11:21
01.97 kB
main.c9.82 kB2014-02-27|11:56
main.h1.86 kB2012-11-15|11:46
Read_Me.txt6.96 kB2013-12-16|21:46
stm32f4xx_conf.h3.71 kB2013-03-05|14:42
stm32f4xx_it.c4.34 kB2013-03-05|12:05
stm32f4xx_it.h2.00 kB2013-03-05|12:06
...
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