Home » Source Code » MPU6050 (hardware IIC) » stm32f10x_cec.c

stm32f10x_cec.c ( File view )

  • By 昱晨 2015-04-27
  • View(s):8
  • Download(s):2
  • Point(s): 0
			/**
  ******************************************************************************
  * @file    stm32f10x_cec.c
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    11-March-2011
  * @brief   This file provides all the CEC firmware functions.
  ******************************************************************************
  * @attention
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_cec.h"
#include "stm32f10x_rcc.h"

/** @addtogroup STM32F10x_StdPeriph_Driver
  * @{

  */

/** @defgroup CEC 
  * @brief CEC driver modules
  * @{

  */

/** @defgroup CEC_Private_TypesDefinitions
  * @{

  */

/**
  * @
}
  */


/** @defgroup CEC_Private_Defines
  * @{

  */ 

/* ------------ CEC registers bit address in the alias region ----------- */
#define CEC_OFFSET                (CEC_BASE - PERIPH_BASE)

/* --- CFGR Register ---*/

/* Alias word address of PE bit */
#define CFGR_OFFSET                 (CEC_OFFSET + 0x00)
#define PE_BitNumber                0x00
#define CFGR_PE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))

/* Alias word address of IE bit */
#define IE_BitNumber                0x01
#define CFGR_IE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))

/* --- CSR Register ---*/

/* Alias word address of TSOM bit */
#define CSR_OFFSET                  (CEC_OFFSET + 0x10)
#define TSOM_BitNumber              0x00
#define CSR_TSOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))

/* Alias word address of TEOM bit */
#define TEOM_BitNumber              0x01
#define CSR_TEOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
  
#define CFGR_CLEAR_Mask            (uint8_t)(0xF3)        /* CFGR register Mask */
#define FLAG_Mask                  ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
 
/**
  * @
}
  */ 


/** @defgroup CEC_Private_Macros
  * @{

  */ 

/**
  * @
}
  */ 


/** @defgroup CEC_Private_Variables
  * @{

  */ 

/**
  * @
}
  */ 


/** @defgroup CEC_Private_FunctionPrototypes
  * @{

  */
 
/**
  * @
}
  */ 


/** @defgroup CEC_Private_Functions
  * @{

  */ 

/**
  * @brief  Deinitializes the CEC peripheral registers to their default reset 
  *         values.
  * @param  None
  * @retval None
  */
void CEC_DeInit(void)
{

  /* Enable CEC reset state */
  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);  
  /* Release CEC from reset state */
  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); 

}


/**
  * @brief  Initializes the CEC peripheral according to the specified 
  *         parameters in the CEC_InitStruct.
  * @param  CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
  *         contains the configuration information for the specified
  *         CEC peripheral.
  * @retval None
  */
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
{

  uint16_t tmpreg = 0;
 
  /* Check the parameters */
  assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); 
  assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
     
  /*---------------------------- CEC CFGR Configuration -----------------*/
  /* Get the CEC CFGR value */
  tmpreg = CEC->CFGR;
  
  /* Clear BTEM and BPEM bits */
  tmpreg &= CFGR_CLEAR_Mask;
  
  /* Configure CEC: Bit Timing Error and Bit Period Error */
  tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);

  /* Write to CEC CFGR  register*/
  CEC->CFGR = tmpreg;
  

}

/**
  * @brief  Enables or disables the specified CEC peripheral.
  * @param  NewState: new state of the CEC peripheral. 
  *     This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void CEC_Cmd(FunctionalState NewState)
{

  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;

  if(NewState == DISABLE)
  {

    /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
    while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
    {

    
}  
  
}  

}

/**
  * @brief  Enables or disables the CEC interrupt.
  * @param  NewState: new state of the CEC interrupt.
  *   This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void CEC_ITConfig(FunctionalState NewState)
{

  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;

}

/**
  * @brief  Defines the Own Address of the CEC device.
  * @param  CEC_OwnAddress: The CEC own address
  * @retval None
  */
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
{

  /* Check the parameters */
  assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));

  /* Set the CEC own address */
  CEC->OAR = CEC_OwnAddress;

}

/**
  * @brief  Sets the CEC prescaler value.
  * @param  CEC_Prescaler: CEC prescaler new value
  * @retval None
  */
void CEC_SetPrescaler(uint16_t CEC_Prescaler)
{

  /* Check the parameters */
  assert_param(IS_CEC_PRESCALER(CEC_Prescaler));

  /* Set the  Prescaler value*/
  CEC->PRES = CEC_Prescaler;

}

/**
  * @brief  Transmits single data through the CEC peripheral.
  * @param  Data: the data to transmit.
  * @retval None
  */
void CEC_SendDataByte(uint8_t Data)
{
  
  /* Transmit Data */
  CEC->TXD = Data ;

}


/**
  * @brief  Returns the most recent received data by the CEC peripheral.
  * @param  None
  * @retval The received data.
  */
uint8_t CEC_ReceiveDataByte(void)
{

  /* Receive Data */
  return (uint8_t)(CEC->RXD);

}

/**
  * @brief  Starts a new message.
  * @param  None
  * @retval None
  */
void CEC_StartOfMessage(void)
{
  
  /* Starts of new message */
  *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;

}

/**
  * @brief  Transmits message with or without an EOM bit.
  * @param  NewState: new state of the CEC Tx End Of Message. 
  *     This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void CEC_EndOfMessageCmd(FunctionalState NewState)
{
   
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  /* The data byte will be transmitted with or without an EOM bit*/
  *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;

}

/**
  * @brief  Gets the CEC flag status
  * @param  CEC_FLAG: specifies the CEC flag to check. 
  *   This parameter can be one of the following values:
  *     @arg CEC_FLAG_BTE: Bit Timing Error
  *     @arg CEC_FLAG_BPE: Bit Period Error
  *     @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
  *     @arg CEC_FLAG_SBE: Start Bit Error
  *     @arg CEC_FLAG_ACKE: Block Acknowledge Error
  *     @arg CEC_FLAG_LINE: Line Error
  *     @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
  *     @arg CEC_FLAG_TEOM: Tx End Of Message 
  *     @arg CEC_FLAG_TERR: Tx Error
  *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
  *     @arg CEC_FLAG_RSOM: Rx Start Of Message
  *     @arg CEC_FLAG_REOM: Rx End Of Message
  *     @arg CEC_FLAG_RERR: Rx Error
  *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
  * @retval The new state of CEC_FLAG (SET or RESET)
  */
FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) 
{

  FlagStatus bitstatus = RESET;
  uint32_t cecreg = 0, cecbase = 0;
  
  /* Check the parameters */
  assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
 
  /* Get the CEC peripheral base address */
  cecbase = (uint32_t)(CEC_BASE);
  
  /* Read flag register index */
  cecreg = CEC_FLAG >> 28;
  
  /* Get bit[23:0] of the flag */
  CEC_FLAG &= FLAG_Mask;
  
  if(cecreg != 0)
  {

    /* Flag in CEC ESR Register */
    CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
    
    /* Get the CEC ESR register address */
    cecbase += 0xC;
  
}
  else
  {

    /* Get the CEC CSR register address */
    cecbase += 0x10;
  
}
  
  if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
  {

    /* CEC_FLAG is set */
    bitstatus = SET;
  
}
  else
  {

    /* CEC_FLAG is reset */
    bitstatus = RESET;
  
}
  
  /* Return the CEC_FLAG status */
  return  bitstatus;

}

/**
  * @brief  Clears the CEC's pending flags.
  * @param  CEC_FLAG: specifies the flag to clear. 
  *   This parameter can be any combination of the following values:
  *     @arg CEC_FLAG_TERR: Tx Error
  *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
  *     @arg CEC_FLAG_RSOM: Rx Start Of Message
  *     @arg CEC_FLAG_REOM: Rx End Of Message
  *     @arg CEC_FLAG_RERR: Rx Error
  *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
  * @retval None
  */
void CEC_ClearFlag(uint32_t CEC_FLAG)
{
 
  uint32_t tmp = 0x0;
  
  /* Check the parameters */
  assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));

  tmp = CEC->CSR & 0x2;
       
  /* Clear the selected CEC flags */
  CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);

}

/**
  * @brief  Checks whether the specified CEC interrupt has occurred or not.
  * @param  CEC_IT: specifies the CEC interrupt source to check. 
  *   This parameter can be one of the following values:
  *     @arg CEC_IT_TERR: Tx Error
  *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
  *     @arg CEC_IT_RERR: Rx Error
  *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
  * @retval The new state of CEC_IT (SET or RESET).
  */
ITStatus CEC_GetITStatus(uint8_t CEC_IT
...
...
(Not finished, please download and read the complete file)
			
...
Expand> <Close

Want complete source code? Download it here

Point(s): 0

Download
0 lines left, continue to read
Sponsored links

File list

Tips: You can preview the content of files by clicking file names^_^
Name Size Date
01.97 kB
01.97 kB
core_cm3.c16.87 kB2010-06-07 10:25
core_cm3.h83.71 kB2011-02-09 14:59
startup_stm32f10x_hd.s15.14 kB2011-03-10 10:52
stm32f10x.h619.08 kB2011-03-10 10:51
system_stm32f10x.c35.70 kB2011-03-10 10:51
system_stm32f10x.h2.04 kB2011-03-10 10:51
01.97 kB
01.97 kB
misc.h8.77 kB2011-03-10 10:47
stm32f10x_adc.h21.18 kB2011-03-10 10:47
stm32f10x_bkp.h7.38 kB2011-03-10 10:47
stm32f10x_can.h26.91 kB2011-03-10 10:47
stm32f10x_cec.h6.42 kB2011-03-10 10:47
stm32f10x_crc.h2.11 kB2011-03-10 10:47
stm32f10x_dac.h14.88 kB2011-03-10 10:47
stm32f10x_dbgmcu.h3.73 kB2011-03-10 10:47
stm32f10x_dma.h20.27 kB2011-03-10 10:47
stm32f10x_exti.h6.66 kB2011-03-10 10:47
stm32f10x_flash.h24.85 kB2011-03-10 10:47
stm32f10x_fsmc.h26.38 kB2011-03-10 10:47
stm32f10x_gpio.h19.70 kB2011-03-10 10:47
stm32f10x_i2c.h29.33 kB2011-03-10 10:47
stm32f10x_iwdg.h3.74 kB2011-03-10 10:47
stm32f10x_pwr.h4.28 kB2011-03-10 10:47
stm32f10x_rcc.h29.74 kB2011-03-10 10:47
stm32f10x_rtc.h3.77 kB2011-03-10 10:47
stm32f10x_sdio.h21.35 kB2011-03-10 10:47
stm32f10x_spi.h17.31 kB2011-03-10 10:47
stm32f10x_tim.h51.20 kB2011-03-10 10:47
stm32f10x_usart.h16.16 kB2011-03-10 10:47
stm32f10x_wwdg.h2.90 kB2011-03-10 10:47
01.97 kB
misc.c6.88 kB2011-03-10 10:47
stm32f10x_adc.c46.09 kB2011-03-10 10:47
stm32f10x_bkp.c8.26 kB2011-03-10 10:47
stm32f10x_can.c44.05 kB2011-03-10 10:47
stm32f10x_cec.c11.38 kB2011-03-10 10:47
stm32f10x_crc.c3.27 kB2011-03-10 10:47
stm32f10x_dac.c18.64 kB2011-03-10 10:47
stm32f10x_dbgmcu.c5.03 kB2011-03-10 10:47
stm32f10x_dma.c28.91 kB2011-03-10 10:47
stm32f10x_exti.c6.80 kB2011-03-10 10:47
stm32f10x_flash.c61.08 kB2011-03-10 10:47
stm32f10x_fsmc.c34.65 kB2011-03-10 10:47
stm32f10x_gpio.c22.68 kB2011-03-11 17:43
stm32f10x_i2c.c44.71 kB2011-03-10 10:47
stm32f10x_iwdg.c4.80 kB2011-03-10 10:47
stm32f10x_pwr.c8.55 kB2011-03-10 10:47
stm32f10x_rcc.c50.07 kB2011-03-10 10:47
stm32f10x_rtc.c8.40 kB2011-03-10 10:47
stm32f10x_sdio.c28.25 kB2011-03-10 10:47
stm32f10x_spi.c29.52 kB2011-03-10 10:47
stm32f10x_tim.c106.60 kB2011-03-10 10:47
stm32f10x_usart.c37.41 kB2011-03-10 10:47
stm32f10x_wwdg.c5.60 kB2011-03-10 10:47
01.97 kB
01.97 kB
systick.hex18.40 kB2013-08-15 19:23
01.97 kB
I2C_MPU6050.c4.69 kB2013-08-15 19:23
I2C_MPU6050.h1.13 kB2013-08-15 19:10
I2C_MPU6050.uvgui.Orange131.20 kB2013-08-15 19:25
I2C_MPU6050.uvgui.flyleaf66.57 kB2012-06-25 20:54
I2C_MPU6050.uvopt10.45 kB2013-08-15 19:25
I2C_MPU6050.uvproj16.56 kB2013-08-15 19:00
JLink497.00 B2012-06-25 20:12
JLinkSettings.ini375.00 B2012-06-24 14:45
delay.c177.00 B2011-08-10 16:44
delay.h98.00 B2011-08-08 21:03
main.c1.48 kB2013-08-15 19:11
stm32f10x_conf.h3.22 kB2012-06-24 22:12
stm32f10x_it.c4.30 kB2011-04-04 19:03
stm32f10x_it.h2.04 kB2011-04-04 19:03
usart1.c5.33 kB2013-08-15 14:40
usart1.h234.00 B2011-08-05 21:11
keilkilll.bat399.00 B2011-04-23 10:24
...
Sponsored links

stm32f10x_cec.c (294.78 kB)

Need 0 point
Your Point(s)
Download Download

Download failed? Click here to download one by one.

Tip: this source code project contains 2 packages, please click the allow button on the browser pop-up dialog,after you click the download button.

▪ Click to download this source code directly

LOGIN

Don't have an account? Register now
Need any help?
Mail to: support@codeforge.com

切换到中文版?

CodeForge Chinese Version
CodeForge English Version

Where are you going?

^_^"Oops ...

Sorry!This guy is mysterious, its blog hasn't been opened, try another, please!
OK

Warm tip!

CodeForge to FavoriteFavorite by Ctrl+D