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Full adder in Verilog

A simple Verilog code for full_adder. It is tested in both simulator and xilinx spartan3E fpga board. ...
  verilog      Verilog     

SPI flash model written by Verilog

M25Pxx ST company SPI flash memory Verilog simulation model, the model correctly describes the behavior of SPI flash memory, including reading, writing and erase operations, can be used to hang outside of the SOC with SPI interface, Verify that the SPI interface....
  verilog      Verilog     

8 bit adder Verilog

hey here is a ise format code for xilinx software Verilog 8 bit fixed point coding use this for example for coding with test bench...
  verilog      Verilog     

code Verilog cordic core

A 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included manual for details...
  verilog      Verilog     

SOPC technology using Verilog create Hello program

SOPC technology FPGA Verilog hardware description language, writing in niosII  program    using Altera chip...
  verilog      VHDL     

Verilog jpeg

This core takes as an input the red, green, and blue pixel values, like from a tiff image file, and creates the JPEG bitstream necessary to build a jpeg image. The core was written in generic, regular Verilog code that can be targeted to any FPGA. The core does not rely on any proprietary IP cores,...
  verilog      Verilog     

Four lights switch of marquee (marquee program in Verilog_hdl languages)

This is a learning Verilog HDL good information, suitable for beginners, explained in detail, from the light into the deep, learning the language, it is a hardware description language for good stuff, good material!...
  verilog      Verilog     

Verilog simulation filters

Verilog procedural simulation filters 16-order using the Adder and multiplier 40KHZ 16-bit into and out...
  verilog      Verilog     

Ledbanner in Verilog code using FPGA SPARTAN-3E

Ledbanner in Verilog code using FPGA SPARTAN-3E is displaying 0-9 in 2 seven segment display.  It will go from left to rigth or vise Versa. And will reset fuction when press reset botton....
  verilog      Verilog     

Veriolg HDL d flip-flop

D trigger program, suits the beginner to use and learn, Verilog HDL languages, using Xillinx's chips....
  verilog      Verilog     

Design module Bluetooth by Verilog

The Bluetooth is a standard protocol for wireless connection between devices such as cell phones, PDAs, PCs and any other device. The main objective for this standard is to provide a royalty free standard for such wireless protocol. The objective of this project is to build an opensource free blueto...
  verilog      Verilog     

adsp m25p16 driVer

ADSP m25p16 driVer code, I personally tested, you can download the trial. Connect the cable, Visual DSP++ Environment loaded in the drive. To download or read the information w25q16....
  Driver Development        C     

Verilog serial program based on ep4ce22

Verilog circuits string mouth procedure based on ep4ce22, you can send 24bit, hoping to provide help....
  verilog      Verilog     

Verilog uart 115200

Using serial port UART transmission module written in Verilog, sending rate to 115200, input clock for 50m for many years validation without errors...
  verilog      Verilog     

ws2801_driVer

;************************************************************************************************ DRIVer_WS2801: ; STAR FOR WS2801 WAIT 500US ;------------------------------------------------------------------------------ CLK_SET_LOW500US: cbi PORTB,WS2801_CLK LDI TEMPA,10 LOOP_WAIT_500US:...
  Driver Development        ASM     

4-bit counters Verilog code

One of the basics of Verilog source code, binary counters for a 4. Both counts can be achieved to realize the frequency of the clock signal, so that is one Very practical introduction to Verilog code. On the basis of this code, you can make a variety of changes, to achieve different functionality....
  verilog      VHDL     

DDR2 controller, Verilog source code

Using Verilog prepared of DDR2 controller, achieved has DDR2 of reads and writes function, in Xilinx vietex5 Shang to achieved, achieved has Imaging algorithm in the of data turn home,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,...
  verilog      Verilog     

Introduction to Verilog

This article introduces the basics of Verilog HDL language, to enable the beginner to quickly grasp the HDL Design methods, preliminary reports and to master the basics of Verilog HDL language, to be able to read simple design code and Enough to make some simple Verilog HDL design modeling...
  verilog      Verilog     

Verilog serial port serial port receive module receiVer module

Verilog serial port serial port receive module receiVer module, contains the BPS modules, level detection module and the control module...
  verilog      Verilog     

Verilog for lsfr oVer bist

When desgin memories with larg portion, which include capacitance oVer bit-lines. The two bit-line are used perform a read and write operation, due to operation of discharging a capacitance in write operation. 7T SRAM cell reduces the activity factor of discharging the bit line pair to perform a...
  verilog      Verilog     

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