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Source-Action part of the station

"Letters" is intended for the convenience of Member business correspondence service, similar to the mailbox, mainly from the Inbox, Outbox, drafts, and trash consists of four parts, but this feature is only open to registered members of the site. "Faith" is different from e-mail, e-mail sent t...
  Web Framework        Java     

ActionScript 3 0

O'Reilly - ActionScript 3 0 Cookbook...
  document        ActionScript     

addCustomer

The application should let a user maintain a list of customers. After selecting a customer the user should be able to specify in what states the customer does business in. By clicking the "Save all changes"-button all the changes made by the user should be stored in a MySQL database. List of clie...
  Other        PHP     

Guestbook code

A JSP application achieve guest book Guest book admin management JavaBean,Taglib, technology For JSP beginner to learn to use...
  Java Development        Java     

Full adder

module full_adder(     output reg sum,     output c_out,   // carry out     input a,     input b,     input c_in);    // carry in      always @(*)        begin       &n...
  add      Verilog     

carry look ahead adder

This is carry look ahead adder which is very useful in order to add 4 bit thing . A carry-lookahead adder (CLA) is a type of adder used in digital logic. A carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits. It can be contrasted with the simpler,...
  vhdl      VHDL     

Cmos Full adders Using Adiabatic Logic

Adiabatic circuits are low power circuits which use "reversible logic" to conserve energy. Unlike traditional CMOS circuits, which dissipate energy during switching, adiabatic circuits attempt to conserve charge by following two key rules: Never turn on a&nbs...
  vhdl      VHDL     

half-adder

it contains half-adder vhdl code and simulate form also, there is test bench coding for half-adder, which means writers can gave a clock by himself. like a <= '0', '1' after 5ns, '0' after 10ns, '1' after 15ns, '0' after 20ns, '1'after 25ns, '0' after 30ns, '1' after 35ns;...
  vhdl      VHDL     

half-adder

it contain VHDL half -adder with test-bench test-bench means 'project maker can announce what time shall he give a term for example a <= '0', '1' after 5ns, '0' after 10ns, '1' after 15ns, '0' after 20ns, '1' after 25ns, '0' after 30ns, '1' 35ns; b <= '0', '1' after 10n...
  vhdl      VHDL     

Online address Book

It is a simple online address Book used to store your contact information on internet. It is developed using codeigniter framework. It contains Registration and Login form....
  Web Framework        HTML/CSS     

TEXT EXTRACTION FROM IMAGES

text extraction from images .... steps to follow the above procedure.. steps : detection localization tracking extraction enhancement recognition (optical character recognition)........
  Image Editing        PDF     

ripple carry adder

it is xilix project. it is generic code for ripple carry adder and its test bench is also their. it has minimum delay. it is checked. its working properly.      ...
  verilog      Verilog     

CMOS FULL-addERS FOR ENERGY-EFFICIENT ARITHMETIC APPLICATIONS

In electronics, an adder or summer is a digital circuit that performs addition of numbers. In many computers and other kinds of processors, adders are used not only in the arithmetic logic unit(s), but also in other parts of the processor,...
  vhdl      VHDL     

Carry ripple adder (16 bit - not use Full adder)

this is a CSA - Carry ripple adder.   for 16 bit   it doesn't run by cascade of full adders.   it all made up of P, G and sum gates....
  Algorithm      Verilog     

addersubtractor

AVIaddXSubs is a simple to use, free program to subtitle videos converting the original srt files you may have. Its services are useful in cases your hardware player is not able to show the subtitles directly from srt or even if it does the result is not satisfactory. Using...
  verilog      Verilog     

Simple Full adder Verilog Code

This is a simple 1 bit full adder verilog code `timescale 1ns / 1ps module 1BitFulladder ( input a, input b, input cin, output s, output cout ); assign s = a ^ b ^ cin; assign cout = (a & b) | (a & cin) | (b & cin); endmodule //Test Bench...
  Verilog      Verilog     

Series of addition

 addtion of 8bit Array in a asembly language programm.  addtion of 8bit Array in a asembly language programm. Explanation: · This program adds two 8 - bit numbers. · The program has been developed using emu80...
  Assembly Language        ASM     

4-bit prallel adder

a>    Half adder module ha(sum,ca,a,b);     input a,b;     output sum,ca;              assign sum= a^b;         &nbs...
  verilog      Verilog     

CMOS FULL-addERS DESIGN USING DPL LOGIC

We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of s...
  verilog      Verilog     

An additive watermarking image based on PSO

Many researchers were used the additive method of digital watermarking images which we quote for example Anuradha and Rudresh Pratap Singh (2006) [1]. However, this paper proposes an additive watermarking method by invoking Particle Swarm Optimization (PSO) technique in wavelet domain to improv...
  Matlab        Matlab     

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