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16 bit risc processor for computer hardware

16 bit risc processor for computer hardware ...
  Algorithm      VHDL     

AXI slave verilog code

Wrote AXI slaver verilog code, hope to give you some inspiration...
  verilog      Verilog     

VGA color display the verilog code for Xilinx FPGA

verilog implementation of FPGA VGA sesser stripes display code, test absolutely right, can successfully implement functionality....
  verilog      Verilog     

4-bit counters verilog code

One of the basics of verilog source code, binary counters for a 4. Both counts can be achieved to realize the frequency of the clock signal, so that is one very practical introduction to verilog code. On the basis of this code, you can make a variety of changes, to achieve different functionality....
  verilog      VHDL     

Parallel CRC verilog code generator

A parllel CRC verilog generator has been written in C++ to generate a parallel CRC verilog code for a given user defined data width and CRC polynomial. This is from outputlogic.com . This a direct implementation algorithm used in the website....
  verilog      Verilog     

Ledbanner in verilog code using FPGA SPARTAN-3E

Ledbanner in verilog code using FPGA SPARTAN-3E is displaying 0-9 in 2 seven segment display.  It will go from left to rigth or vise versa. And will reset fuction when press reset botton....
  verilog      Verilog     

verilog code for 8 bit array multiplier

I have written verilog for 8 bit array multiplier . Accepts two 8 bit numbers and gives 16 bit result....
  verilog      VHDL     

DESIGN OF 32 bit CARRY-LOOK AHEAD ADDER

In this paper design of 32 bit carry look ahead adder is done .the complexity is reduced by designing 8 4 bit cla block.  ...
  verilog      Verilog     

verilog code for the GPS baseband processing

GPS software receiver baseband processing verilog programs, by spread spectrum demodulation, intermediate frequency data synchronization process converts the raw navigation data...
  verilog      Verilog     

32 processor> example code

<embedded real-time operating system μC/OS-Ⅱ classical examples- based on STM32 processor> example code, is the source code of the examples in this book, it is very helpful for μ-C/OS-II and the STM32 beginners, also can be used as reference to project development....
  STM32        C     

verilog code for ECC processor using karatsuba multiplier

We are working on a project based on side channel attacks caused in a ECC processor while performing multiplication....
  verilog      Verilog     

verilog code for vedic multiplier

This is the source code for 8x8 vedic multiplier is designed by ancient vedic mathematics. It contains 16 sutra in that urdhva tiryagbhyam suytra is used. For the addition operation full adder is used ....
  verilog      Verilog     

IEEE 754 32 bit - MATLAB

The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a technical standard for floating-point computation established in 1985 by the Institute of Electrical and Electronics Engineers(IEEE). Many hardware floating point units use the IEEE 754 stan...
  Matlab        Matlab     

verilog code for SDRAM

SDRAM driver, written in the verilog language, verilog reference those things is coming from, and is divided into three modules, initialize the module, the function module and the control module, the module which has a total of three modules together. 4bank row width column widths are 12-8-bit SDRAM...
  Driver Development      Verilog     

verilog jpeg

This core takes as an input the red, green, and blue pixel values, like from a tiff image file, and creates the JPEG bitstream necessary to build a jpeg image. The core was written in generic, regular verilog code that can be targeted to any FPGA. The core does not rely on any proprietary IP cores,...
  verilog      Verilog     

Full adder in verilog

A simple verilog code for full_adder. It is tested in both simulator and xilinx spartan3E fpga board. ...
  verilog      Verilog     

risc Microcontroller

riscMCU is based on the features and instruction set of Atmel AVR AT90S1200 risc Microcontroller. The aim of the project is to design the complete Atmel AVR AT90S1200. The microcontroller must be able to fit into the targeted FPGA device, which is Altera EPF10K20, provided in Altera UP1 Edu...
  verilog      Verilog     

8 bit adder verilog

hey here is a ise format code for xilinx software verilog 8 bit fixed point coding use this for example for coding with test bench...
  verilog      Verilog     

verilog for booth multiplier

We are going to propose a new SRAM bitcell for the purpose of less power consumption, read stability,less area than the existing Schmitt trigger based SRAM and other existing designs through a new design which is combined of virtual grounding with Read error reduction logic.  ...
  verilog      Verilog     

Simple Full Adder verilog code

This is a simple 1 bit full adder verilog code `timescale 1ns / 1ps module 1bitFullAdder ( input a, input b, input cin, output s, output cout ); assign s = a ^ b ^ cin; assign cout = (a & b) | (a & cin) | (b & cin); endmodule //Test Bench...
  Verilog      Verilog     

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