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16 bit risc processor for computer hardware

16 bit risc processor for computer hardware ...
  Algorithm      VHDL     

4-bit counters verilog code

One of the basics of verilog source code, binary counters for a 4. Both counts can be achieved to realize the frequency of the clock signal, so that is one very practical introduction to verilog code. On the basis of this code, you can make a variety of changes, to achieve different functionality....
  verilog      VHDL     

Ledbanner in verilog code using FPGA SPARTAN-3E

Ledbanner in verilog code using FPGA SPARTAN-3E is displaying 0-9 in 2 seven segment display.  It will go from left to rigth or vise versa. And will reset fuction when press reset botton....
  verilog      Verilog     

verilog code for the GPS baseband processing

GPS software receiver baseband processing verilog programs, by spread spectrum demodulation, intermediate frequency data synchronization process converts the raw navigation data...
  verilog      Verilog     

32 processor> example code

<embedded real-time operating system μC/OS-Ⅱ classical examples- based on STM32 processor> example code, is the source code of the examples in this book, it is very helpful for μ-C/OS-II and the STM32 beginners, also can be used as reference to project development....
  STM32        C     

IEEE 754 32 bit - MATLAB

The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a technical standard for floating-point computation established in 1985 by the Institute of Electrical and Electronics Engineers(IEEE). Many hardware floating point units use the IEEE 754 stan...
  Matlab        Matlab     

Full adder in verilog

A simple verilog code for full_adder. It is tested in both simulator and xilinx spartan3E fpga board. ...
  verilog      Verilog     

risc Microcontroller

riscMCU is based on the features and instruction set of Atmel AVR AT90S1200 risc Microcontroller. The aim of the project is to design the complete Atmel AVR AT90S1200. The microcontroller must be able to fit into the targeted FPGA device, which is Altera EPF10K20, provided in Altera UP1 Edu...
  verilog      Verilog     

verilog for booth multiplier

We are going to propose a new SRAM bitcell for the purpose of less power consumption, read stability,less area than the existing Schmitt trigger based SRAM and other existing designs through a new design which is combined of virtual grounding with Read error reduction logic.  ...
  verilog      Verilog     

Simple Full Adder verilog code

This is a simple 1 bit full adder verilog code `timescale 1ns / 1ps module 1bitFullAdder ( input a, input b, input cin, output s, output cout ); assign s = a ^ b ^ cin; assign cout = (a & b) | (a & cin) | (b & cin); endmodule //Test Bench...
  Verilog      Verilog     

SPI flash model written by verilog

M25Pxx ST company SPI flash memory verilog simulation model, the model correctly describes the behavior of SPI flash memory, including reading, writing and erase operations, can be used to hang outside of the SOC with SPI interface, verify that the SPI interface....
  verilog      Verilog     

verilog LED spartan 6

This code is the verilog code, and spartan 6 model specification code. Welcome to download and try. Thank you for your support....
  verilog      Verilog     

SOPC technology using verilog create Hello program

SOPC technology FPGA verilog hardware description language, writing in niosII  program    using Altera chip...
  verilog      VHDL     

classics_verilog_codes_for_commom_projects

it contains a mass  of classics verilog codes for common projects,such as FIFO, add8, RS coding, multiplexing,and so on. these verilog codes are all very basic but extensive, which must be a great help for beginners who learn verilog. it will help beginner to control verilog languar...
  verilog      Verilog     

verilog for lsfr over bist

When desgin memories with larg portion, which include capacitance over bit-lines. The two bit-line are used perform a read and write operation, due to operation of discharging a capacitance in write operation. 7T SRAM cell reduces the activity factor of discharging the bit line pair to perform a...
  verilog      Verilog     

verilog simulation filters

verilog procedural simulation filters 16-order using the Adder and multiplier 40KHZ 16-bit into and out...
  verilog      Verilog     

code verilog for motion compensated prediction block of video

This is a project about VLSI design.Topic is design for motion compensated prediction block in compressed video.Project consisted code RTL,code Testbench.  Project use software of synopsys for example: Design Compiler (Synthesis),IC Compiler (Layout)......
  verilog      Verilog     

"Original" display __ __verilog_ _FPGA control _1602 debugging notes

FPGA control principle and LCD1602 debugging notes source code This information came from Baidu bases (http://wenku.Baidu.com/) You now see the document is used to hold rice Baidu base generated by the Download Manager This document's original address from Thank you for your support Hold rice...
  verilog      Verilog     

DDS_Dual_ports verilog implementation

DDS_Dual_ports verilog implementation, you need to download experiment, according to their own needs to be modified in order to achieve the purpose of its...
  verilog      Verilog     

verilog serial port serial port receive module receiver module

verilog serial port serial port receive module receiver module, contains the BPS modules, level detection module and the control module...
  verilog      Verilog     

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