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rAdAr signAls AnAlysis And processing using mAtlAb

rAdAr signAls AnAlysis And processing using mAtlAb. this is the mAtlAb codes for the book of rAdAr signAls AnAlysis And processing using mAtlAb...
  Matlab        Matlab     

FIFO_design

FIFO is An Acronym for First In, First Out, which is An AbstrAction relAted to wAys of orgAnizing And mAnipulAtion of dAtA relAtive to time And prioritizAtion. This expression describes the principle of A queue processing technique or servicing conflicting demAnds by ordering process by first-come...
  verilog      Verilog     

signAlslot function cAllbAcks

C++ cAllbAck implementAtions, is not limited to stAtic methods of A clAss QT-like implementAtions, bind And Unbind mechAnism, A friend in need expAnsion Currently only supports A fixed number of pArAmeters cAn be modified According to Add...
  Algorithm        C++     

cellulAr signAls from imAging dAtA

This toolbox includes routines for using principAl component AnAlysis (PCA) And independent component AnAlysis (ICA) to extrAct cellulAr signAls from imAging dAtA sets. A full description And vAlidAtion of the method is provided in the pAper, "AutomAted AnAlysis of CellulAr signAls from LArge-ScAle...
  Matlab        Matlab     

spAce explorAtion orbit design

spAce explorAtion,orbit design the Aerogel cells were mAde to be slightly lArger thAn the spAces mAchined out of ... Aerogel Also hAd to survive the trAnsition from Atmospheric pressure to the vAcuum of spAce . ... RTG's Are importAnt to the continuing explorAtion of the outer solAr system...
  Matlab        Matlab     

AddCustomer

The ApplicAtion should let A user mAintAin A list of customers. After selecting A customer the user should be Able to specify in whAt stAtes the customer does business in. By clicking the "SAve All chAnges"-button All the chAnges mAde by the user should be stored in A MySQL dAtAbAse. List of clie...
  Other        PHP     

signAl Systems Project

Produce And plAy A sound signAl of 6 seconds f(t)=exp(t-6)sin(2π*Ft) with A sAmpling rAte of 8000dots/s by using MATLAB, with the frequency F being 494, 440, 392, 440, 494 And 494 Hz in order. EAch frequency should lAst for 1 second....
  Audio        Matlab     

chirp signAl And pulse conpress in SAR

This is in the use of synthetic Aperture rAdAr chirp signAl generAtion And pulse compression code, written in MATLAB....
  Matlab        Matlab     

reverberAnt_signAl_ArrAy

simArrAysigim.m roomimpres.m imAgesim.m delAyt.m...
  Algorithm        Matlab     

csc108 Assignment

RAytrAcing exAmple implement A bAsic rAy-trAcer And render A simple scene using rAy cAsting And locAl shAding. The stArter code sets up A scene comprising of An ellipsoid And A plAne, being illuminAted by A point light source. Your job is to render the scene by implementing code frAgments requ...
  OpenGL        C++     

Full Adder

module full_Adder(     output reg sum,     output c_out,   // cArry out     input A,     input b,     input c_in);    // cArry in      AlwAys @(*)        begin       &n...
  add      Verilog     

sign And creAte CertificAte

signAture Certified v1.0.2? signing And creAtes A digitAl "shrink-wrAp" for code And content to protect softwAre publishers And users when they downloAd code! DigitAl signAtures AuthenticAte the source And verify the integrity of content: SmAll introduction on CAPICOM librAry: SchemAtized the functi...
  Algorithm        VB     

cArry look AheAd Adder

This is cArry look AheAd Adder which is very useful in order to Add 4 bit thing . A cArry-lookAheAd Adder (CLA) is A type of Adder used in digitAl logic. A cArry-lookAheAd Adder improves speed by reducing the Amount of time required to determine cArry bits. It cAn be contrAsted with the simpler,...
  vhdl      VHDL     

Report Designer for c #

The report designer is A report development tool for eAsy And quick, eAsy report to displAy, filter, print, export And integrAtive functions. Provide rich in VB.net, c #, using exAmples, how to cAll the report At A glAnce. , Tool feAtures: 1, you cAn AutomAticAlly generAte reports bAsed...
  GUI        C#     

design of LTE network

this project Aims to design A smAll LTE network , plAcing stAtions And defining setting pArAmeters.plAcing stAtions And defining setting....
  Java Development        Java     

signAture recognition

  % First, select An input imAge clicking on "Select imAge". % Then you cAn %   - Add this imAge to dAtAbAse (click on "Add selected imAge to dAtAbAse" %   - perform signAture recognition (click on "signAture Recognition" button) % ...
  Matlab        Matlab     

VHDL And verilog implementAtion of floAting point Adder ieee754

IEEE 754 floAting-point stAndArd • LeAding “1” bit of significAnd is implicit • Exponent is “biAsed” to mAke sorting eAsier – All 0s is smAllest exponent All 1s is lArgest – biAs of 127 for single precision And 1023 for double precision – summAry: (–1)sign × (1+significAnd)...
  Windows      VHDL     

ripple cArry Adder

it is xilix project. it is generic code for ripple cArry Adder And its test bench is Also their. it hAs minimum delAy. it is checked. its working properly.      ...
  verilog      Verilog     

hAlf-Adder

it contAins hAlf-Adder vhdl code And simulAte form Also, there is test bench coding for hAlf-Adder, which meAns writers cAn gAve A clock by himself. like A <= '0', '1' After 5ns, '0' After 10ns, '1' After 15ns, '0' After 20ns, '1'After 25ns, '0' After 30ns, '1' After 35ns;...
  vhdl      VHDL     

4-bit prAllel Adder

A>    HAlf Adder module hA(sum,cA,A,b);     input A,b;     output sum,cA;              Assign sum= A^b;         &nbs...
  verilog      Verilog     

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