library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
Library UNISIM;
use UNISIM.vcomponents.all;
--------------------------------------------------------------------... signal ProcessingVHDL
v1.13 (10/19/2012)
+ Increased the BDF font merger function.
+ To increase automatic calibration baseline function.
+ Added support BDF V2.2.
* Improve the Vietnamese unicode encoded font (increase spreading codes and VerifyCode)
v1.12 (09/17/2012)
+ Incre... 应用软件Visual C++
big screen led to the dot matrix display driver timing. The use of VHDL description language. Rom which documents can be automatically generated using lpm_megcore.... VHDL-FPGA-VerilogOthers
32* 32 dot-matrix program, set up the typewriter font size type
32* 32 dot-matrix program, set up the typewriter font size type... Other Embeded programC++