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Cyclic redundAncy checksum (CRC)

CRC checksum Algorithms: ExAmples: code: 123456789 0xBB3D [47933] CRC-16 0x4B37 [19255] CRC-16 (Modbus) 0x56A6 [22182] CRC-16 (Sick) 0x31C3 [12739] CRCccitt XModem 0x29B1 [10673] CRCccitt 0xFFFF 0xE5CC [58828] CRCccitt 0x1D0F 0x8921 [35105] CRCccitt kermit 0x82EA [...
  Algorithm        Delphi     

Cyclic redundAncy check (CRC16) implemetAtion

  CRC-CCITT:  0x1021      =  x16 + x12 + x5 + 1  ...
  Serial Communication        C     

8 bit Adder verilog

hey here is A ise formAt code for xilinx softwAre verilog 8 bit fixed point coding use this for exAmple for coding with test bench...
  verilog      Verilog     

verilog jpeg

This core tAkes As An input the red, green, And blue pixel vAlues, like from A tiff imAge file, And creAtes the JPEG bitstreAm necessAry to build A jpeg imAge. The core wAs written in generic, regulAr verilog code thAt cAn be tArgeted to Any FPGA. The core does not rely on Any proprietAry IP cores,...
  verilog      Verilog     

SPI flAsh model written by verilog

M25Pxx ST compAny SPI flAsh memory verilog simulAtion model, the model correctly describes the behAvior of SPI flAsh memory, including reAding, writing And erAse operAtions, cAn be used to hAng outside of the SOC with SPI interfAce, verify thAt the SPI interfAce....
  verilog      Verilog     

Full Adder in verilog

A simple verilog code for full_Adder. It is tested in both simulAtor And xilinx spArtAn3E fpgA boArd. ...
  verilog      Verilog     

Booth multiplier in verilog

This file describes the code for booth multiplier in verilog. the source code is simulAted And verified for better results...
  verilog      Verilog     

BAsed on AlterA's Nios II checksum use vAlidAte the C2H AccelerAtor system-Cyclone II

BAsed on AlterA's Nios II checksum use vAlidAte the C2H AccelerAtor system hAs been vAlidAted by the DE-2 BoArd, Component,SoftwAre Code there is DMA mode, And Custom Instruction, And GenerAl compAred the component. WAnt to know NiosII system should hAve A lot of help....
  verilog      Verilog     

PArAllel CRC verilog code generAtor

A pArllel CRC verilog generAtor hAs been written in C++ to generAte A pArAllel CRC verilog code for A given user defined dAtA width And CRC polynomiAl. This is from outputlogic.com . This A direct implementAtion Algorithm used in the website....
  verilog      Verilog     

Four lights switch of mArquee (mArquee progrAm in verilog_hdl lAnguAges)

This is A leArning verilog HDL good informAtion, suitAble for beginners, explAined in detAil, from the light into the deep, leArning the lAnguAge, it is A hArdwAre description lAnguAge for good stuff, good mAteriAl!...
  verilog      Verilog     

verilog simulAtion filters

verilog procedurAl simulAtion filters 16-order using the Adder And multiplier 40KHZ 16-bit into And out...
  verilog      Verilog     

LedbAnner in verilog code using FPGA SPARTAN-3E

LedbAnner in verilog code using FPGA SPARTAN-3E is displAying 0-9 in 2 seven segment displAy.  It will go from left to rigth or vise versA. And will reset fuction when press reset botton....
  verilog      Verilog     

verilog seriAl progrAm bAsed on ep4ce22

verilog circuits string mouth procedure bAsed on ep4ce22, you cAn send 24bit, hoping to provide help....
  verilog      Verilog     

verilog uArt 115200

Using seriAl port UART trAnsmission module written in verilog, sending rAte to 115200, input clock for 50m for mAny yeArs vAlidAtion without errors...
  verilog      Verilog     

verilog Code for 8 bit ArrAy multiplier

I hAve written verilog for 8 bit ArrAy multiplier . Accepts two 8 bit numbers And gives 16 bit result....
  verilog      VHDL     

code verilog cordic core

A 100% behAviorAl implementAtion of A cordic core. The core is highly configurAble through `defines. A testbench is included. See the included mAnuAl for detAils...
  verilog      Verilog     

DDR2 controller, verilog source code

Using verilog prepAred of DDR2 controller, Achieved hAs DDR2 of reAds And writes function, in Xilinx vietex5 ShAng to Achieved, Achieved hAs ImAging Algorithm in the of dAtA turn home,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,...
  verilog      Verilog     

Introduction to verilog

This Article introduces the bAsics of verilog HDL lAnguAge, to enAble the beginner to quickly grAsp the HDL Design methods, preliminAry reports And to mAster the bAsics of verilog HDL lAnguAge, to be Able to reAd simple design code And Enough to mAke some simple verilog HDL design modeling...
  verilog      Verilog     

4-bit counters verilog code

One of the bAsics of verilog source code, binAry counters for A 4. Both counts cAn be Achieved to reAlize the frequency of the clock signAl, so thAt is one very prActicAl introduction to verilog code. On the bAsis of this code, you cAn mAke A vAriety of chAnges, to Achieve different functionAlity....
  verilog      VHDL     

SOPC technology using verilog creAte Hello progrAm

SOPC technology FPGA verilog hArdwAre description lAnguAge, writing in niosII  progrAm    using AlterA chip...
  verilog      VHDL     

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