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Cyclic redundAncy checksum (CRC)

CRC checksum Algorithms: ExAmples: code: 123456789 0xBB3D [47933] CRC-16 0x4B37 [19255] CRC-16 (Modbus) 0x56A6 [22182] CRC-16 (Sick) 0x31C3 [12739] CRCccitt XModem 0x29B1 [10673] CRCccitt 0xFFFF 0xE5CC [58828] CRCccitt 0x1D0F 0x8921 [35105] CRCccitt kermit 0x82EA [...
  Algorithm        Delphi     

Cyclic redundAncy check (CRC16) implemetAtion

  CRC-CCITT:  0x1021      =  x16 + x12 + x5 + 1  ...
  Serial Communication        C     

SPI flAsh model written by verilog

M25Pxx ST compAny SPI flAsh memory verilog simulAtion model, the model correctly describes the behAvior of SPI flAsh memory, including reAding, writing And erAse operAtions, cAn be used to hAng outside of the SOC with SPI interfAce, verify thAt the SPI interfAce....
  verilog      Verilog     

Full Adder in verilog

A simple verilog code for full_Adder. It is tested in both simulAtor And xilinx spArtAn3E fpgA boArd. ...
  verilog      Verilog     

Four lights switch of mArquee (mArquee progrAm in verilog_hdl lAnguAges)

This is A leArning verilog HDL good informAtion, suitAble for beginners, explAined in detAil, from the light into the deep, leArning the lAnguAge, it is A hArdwAre description lAnguAge for good stuff, good mAteriAl!...
  verilog      Verilog     

verilog simulAtion filters

verilog procedurAl simulAtion filters 16-order using the Adder And multiplier 40KHZ 16-bit into And out...
  verilog      Verilog     

LedbAnner in verilog code using FPGA SPARTAN-3E

LedbAnner in verilog code using FPGA SPARTAN-3E is displAying 0-9 in 2 seven segment displAy.  It will go from left to rigth or vise versA. And will reset fuction when press reset botton....
  verilog      Verilog     

DDR2 controller, verilog source code

Using verilog prepAred of DDR2 controller, Achieved hAs DDR2 of reAds And writes function, in Xilinx vietex5 ShAng to Achieved, Achieved hAs ImAging Algorithm in the of dAtA turn home,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,...
  verilog      Verilog     

Introduction to verilog

This Article introduces the bAsics of verilog HDL lAnguAge, to enAble the beginner to quickly grAsp the HDL Design methods, preliminAry reports And to mAster the bAsics of verilog HDL lAnguAge, to be Able to reAd simple design code And Enough to mAke some simple verilog HDL design modeling...
  verilog      Verilog     

4-bit counters verilog code

One of the bAsics of verilog source code, binAry counters for A 4. Both counts cAn be Achieved to reAlize the frequency of the clock signAl, so thAt is one very prActicAl introduction to verilog code. On the bAsis of this code, you cAn mAke A vAriety of chAnges, to Achieve different functionAlity....
  verilog      VHDL     

SOPC technology using verilog creAte Hello progrAm

SOPC technology FPGA verilog hArdwAre description lAnguAge, writing in niosII  progrAm    using AlterA chip...
  verilog      VHDL     

DDS_DuAl_ports verilog implementAtion

DDS_DuAl_ports verilog implementAtion, you need to downloAd experiment, According to their own needs to be modified in order to Achieve the purpose of its...
  verilog      Verilog     

FloAting-point multiply verilog FPGA

DigitAl multiplier, As An integrAl pArt of modern computers, their design work And more And more people's Attention. This pAper, hArdwAre description lAnguAges verilog HDL design A floAting-point multiplier bAsed on complement one multiplicAtion And design functions And better flexibility. Th...
  verilog      Verilog     

I2C verilog

I2C verilog files. Define A simple interfAce of I2C. After testing to ensure the using....
  verilog      Verilog     

verilog seriAl port seriAl port receive module receiver module

verilog seriAl port seriAl port receive module receiver module, contAins the BPS modules, level detection module And the control module...
  verilog      Verilog     

8,051 nucleAr verilog source code

8,051 core RTL source code, with integrAted testbench And scripts 8,051 core RTL source code, with integrAted testbench And scripts 8,051 core RTL source code, with integrAted testbench And scripts 8,051 core RTL source code, with integrAted testbench And scripts 8,051 core R...
  verilog        ASM     

Using FPGA verilog HDL simulAtion clAss I2C communicAtion

Using FPGA verilog HDL simulAtion clAss I2C communicAtion...
  verilog      Verilog     

PLL LMX2531 verilog ConfigurAtor

Source verilog progrAmming, registers Are used for configuring the PLL LMX2531, the output frequency is 1 GHz, hAs proven the vAlue of the register, the clock output frequencies without problems, written with three-stAte mAchines, incidentAlly, one AD device configured, refer the reAder to key refer...
  verilog      Verilog     

"OriginAl" displAy __ __verilog_ _FPGA control _1602 debugging notes

FPGA control principle And LCD1602 debugging notes source code This informAtion cAme from BAidu bAses (http://wenku.BAidu.com/) You now see the document is used to hold rice BAidu bAse generAted by the DownloAd MAnAger This document's originAl Address from ThAnk you for your support Hold rice...
  verilog      Verilog     

verilog code for the GPS bAsebAnd processing

GPS softwAre receiver bAsebAnd processing verilog progrAms, by spreAd spectrum demodulAtion, intermediAte frequency dAtA synchronizAtion process converts the rAw nAvigAtion dAtA...
  verilog      Verilog     

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