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DE2_115_TV Development Board routines, including SDRAM and asynchronous FIFO

DE2_115_TV Development Board routines, including SDRAM and application of asynchronous FIFO: through coordinated control 2 in 2 out of a total of 4 FIFO operation SDRAM...
  verilog      Verilog     

FIFO IP core calls and simulation

FIFO IP calls in our project can shorten design cycles, eliminates the complex process of writing code, but also eliminates the complexity of the debugger and the complexity of the code. This little simple FIFO IP core called to make it clear for everyone to understand FIFO principle and method call...
  verilog      Verilog     

C++ implementation of synchronous FIFO

Compare with hardware implementation, you can send and receive data in the routing algorithm. Simple modeling models, it is very helpful. Documentation: FIFO.H,FIFO. CPP,MAIN. CPP...
  Other        C++     

Synchronous FIFO state machine implementation

Simple synchronous FIFO state machine description, including read/write counters, empty full flag control. Can achieve sequential read and write data, including the test file, the simulation results. filelist:FIFO.v,FIFO_test.v...
  verilog      Verilog     

USB slave FIFO firmware

this is a sourcecode of USB  slave FIFO firmware...
  Assembly Language        ASM     

FIFO page replacement algorithm

× FIFO page replacement algorithms For example: process P 有 5 pages processes from accessing the page order: 1 , 2 , 3 , 4 , 1 , 2 , 5 , 1 , 2 , 3 , 4 , 5 If assigned to the in-memory processes 3 pages are missing pages...
  Windows        C++     

aynchronous FIFO project

First-In First-Out (FIFO) memory structures are widely used to buffer the transfer of data between processing blocks. High performance and high complexity digital systems increasingly are required to transfer data between modules of differing and even unrelated clock frequencies. The dual-clock...
  verilog      Verilog     

FIFO_design

FIFO is an acronym for First In, First Out, which is an abstraction related to ways of organizing and manipulation of data relative to time and prioritization. This expression describes the principle of a queue processing technique or servicing conflicting demands by ordering process by first-come...
  verilog      Verilog     

Java Web projects page general implementation

General implementation for Java Web projects page page from SSH Framework implementation, the code structure is clear, can be used as a public module, very good. Helpful to new J2EE...
  Java Development        Java     

UART Verilog sorce code and Simulation code and FIFO code

 It is programed by verilog language and main code is UART, The main source code are uart_receiver.v /uart_transmitter.v/lpm_mux0.v/myFIFO.v....... some wave file can help you understand more simulation information....
  verilog      Verilog     

异步FIFO

这是一个异步的FIFO模块,还有5个部分,比较器,写满读空状态标志,和一个RAM模块,是编写一些大型程序的基础模块。谢谢大家,期望大家能够用得着...
  verilog      Verilog     

FIFO_seperate_clock

It is a normal FIFO programing code. where both Read and Write Clock are different. for writing process  reading process seperate pointers used and for controling both process 3 additional pointers are used 1 pointer for write pointer control other for read pointer...
  vhdl      VHDL     

先进先出FIFO协议仿真

The model contains three modules. The "gen" module generates jobs, and sends them to the "FIFO" module which is a single-server queue. Jobs are stored in a queue (cQueue object) until they are served -- this queue can be found and inspected in the graphical environment among the class members of...
  Algorithm        C++     

跨时钟域的异步FIFO设计

跨时钟域的异步FIFO设计设计一个FIFO是ASIC设计者遇到的最普遍的问题之一。本文着重介绍怎 样设计FIFO——这是一个看似简单却很复杂的任务。    一开始,要注意,FIFO通常用于时钟域的过渡,是双时钟设计。换句话说...
  verilog      Verilog     

async FIFO

`timescale 1ns/1ps   13   14 module aFIFO   15   #(parameter    DATA_WIDTH    = 8,   16                  ADDRESS_WIDTH = 4,   17  &nbs...
  verilog      Verilog     

verification environment to verify synchronous FIFO

-> verification environment of synchronous FIFO. -> universal verification methodology used. -> Assertion based verification. -> perl script included to run environment....
  verilog      Verilog     

自定义IP-FIFO

该程序模块详细介绍了自定义缓存模块FIFO的设计过程,正在学习自定义FIFO模块并挂载在avalon总线上用作缓存的读者可参考该程序。...
  Embeded      Verilog     

C#下漂亮的Tabpage

一个在WinForm下使用的TabControl控件,支持Office2007,chrome等多种界面风格。支持Tabpage页面的新建和关闭,界面非常美观,可以生成DLL或者直接在项目中包含控件源码....
  Windows        C#     

pager-taglib

这是pager-taglib的官方源码,但在采用官方的pager-taglib分页传输中文参数会出现乱码,所以我采用maven新建一个pager-taglib项目对pager-taglib的源码进行小小的改动,是他支持中文传输,更重要的是把源代码提供给大家,以便可以根据...
  Java Development        Java     

SlidingMenu Viewpager+Fragment的结合使用

1.首先,将Slidingmenu源码简化,直接应用在项目中。代码精简 2.实现了Slidingmenu滑动界面 3.将Viewpager与Fragment结合在一起 4.将ListFragment运用到项目中...
  Android        Java     

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