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pagerank Algorithm

pageRank is a link analysis algorithm and it assigns a numerical weighting to each element of a hyperlinked set of documents, such as theWorld Wide Web, with the purpose of "measuring" its relative importance within the set. The algorithm may be applied t...
  Algorithm        Java     

DE2_115_TV Development Board routines, including SDRAM and asynchronous FIFO

DE2_115_TV Development Board routines, including SDRAM and application of asynchronous FIFO: through coordinated control 2 in 2 out of a total of 4 FIFO operation SDRAM...
  verilog      Verilog     

FIFO IP core calls and simulation

FIFO IP calls in our project can shorten design cycles, eliminates the complex process of writing code, but also eliminates the complexity of the debugger and the complexity of the code. This little simple FIFO IP core called to make it clear for everyone to understand FIFO principle and method call...
  verilog      Verilog     

C++ implementation of synchronous FIFO

Compare with hardware implementation, you can send and receive data in the routing algorithm. Simple modeling models, it is very helpful. Documentation: FIFO.H,FIFO. CPP,MAIN. CPP...
  Other        C++     

Synchronous FIFO state machine implementation

Simple synchronous FIFO state machine description, including read/write counters, empty full flag control. Can achieve sequential read and write data, including the test file, the simulation results. filelist:FIFO.v,FIFO_test.v...
  verilog      Verilog     

USB slave FIFO firmware

this is a sourcecode of USB  slave FIFO firmware...
  Assembly Language        ASM     

FIFO page replacement algorithm

× FIFO page replacement algorithms For example: process P 有 5 pages processes from accessing the page order: 1 , 2 , 3 , 4 , 1 , 2 , 5 , 1 , 2 , 3 , 4 , 5 If assigned to the in-memory processes 3 pages are missing pages...
  Windows        C++     

aynchronous FIFO project

First-In First-Out (FIFO) memory structures are widely used to buffer the transfer of data between processing blocks. High performance and high complexity digital systems increasingly are required to transfer data between modules of differing and even unrelated clock frequencies. The dual-clock...
  verilog      Verilog     

FIFO_design

FIFO is an acronym for First In, First Out, which is an abstraction related to ways of organizing and manipulation of data relative to time and prioritization. This expression describes the principle of a queue processing technique or servicing conflicting demands by ordering process by first-come...
  verilog      Verilog     

C network programming example (minissh, Webget, NFC, NetLink, net-FIFO)

Some network programming examples: minissh, webget, nfc, netlink, etc......
  TCP/IP        C     

FIFO seperate clock

It is a normal FIFO programing code.where both Read and Write Clock are different for writing process  reading process seperate pointers used and for controling both process 3 additional pointers are used 1 pointer for write pointer control other for read pointer control&nbs...
  vhdl      VHDL     

Java Web projects page general implementation

General implementation for Java Web projects page page from SSH Framework implementation, the code structure is clear, can be used as a public module, very good. Helpful to new J2EE...
  Java Development        Java     

UART Verilog sorce code and Simulation code and FIFO code

 It is programed by verilog language and main code is UART, The main source code are uart_receiver.v /uart_transmitter.v/lpm_mux0.v/myFIFO.v....... some wave file can help you understand more simulation information....
  verilog      Verilog     

Some source codes for webpage navigation, file download, user login

Suitable for beginners, module development of common modules. Includes page navigation, file downloads, user login modules, custom classes, and moving animation module....
  Web Framework        C#     

异步FIFO

这是一个异步的FIFO模块,还有5个部分,比较器,写满读空状态标志,和一个RAM模块,是编写一些大型程序的基础模块。谢谢大家,期望大家能够用得着...
  verilog      Verilog     

先进先出FIFO协议仿真

The model contains three modules. The "gen" module generates jobs, and sends them to the "FIFO" module which is a single-server queue. Jobs are stored in a queue (cQueue object) until they are served -- this queue can be found and inspected in the graphical environment among the class members of...
  Algorithm        C++     

跨时钟域的异步FIFO设计

跨时钟域的异步FIFO设计设计一个FIFO是ASIC设计者遇到的最普遍的问题之一。本文着重介绍怎 样设计FIFO——这是一个看似简单却很复杂的任务。    一开始,要注意,FIFO通常用于时钟域的过渡,是双时钟设计。换句话说...
  verilog      Verilog     

async FIFO

`timescale 1ns/1ps   13   14 module aFIFO   15   #(parameter    DATA_WIDTH    = 8,   16                  ADDRESS_WIDTH = 4,   17  &nbs...
  verilog      Verilog     

FIFO path rtl design and property

Mini Design Describe 4 to 1 buffered multiplexer with arbitration and FIFO bypass  This design is a buffered 4 to 1 data packet multiplexer with arbitration and FIFO bypass. It receives data on 4 input ports and sends data out on 1 output port. Each of the 4 input paths is model...
  verilog      Verilog     

verification environment to verify synchronous FIFO

-> verification environment of synchronous FIFO. -> universal verification methodology used. -> Assertion based verification. -> perl script included to run environment....
  verilog      Verilog     

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