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FP-Growth java code

FP-Growth java code When compiled the software can be invoked in the normal manner using the Java interpreter: java APPLICATION_CLASS_FILE_NAME If you are planning to process a very large data set it is a good idea to grab some extra memory. For example: java -Xms600m...
  Java Development        Java     

weka Genetic Programming

To the right of the status box is the weka status icon. When no processes are running, the bird sits down and takes a nap. The number beside the × symbol gives the number of concurrent processes running. When the system is idle it is zero, but it increases as the number of processes increases. W...
  Java Development        Java     

Matlab to weka converter source code

This code will convert a weka supported file into .mat file and also a matlab file into weka supported file. Using this code, you need not to write separate matlab code for a dataset. Just provide the dataset and you can get its .mat file.  ...
  Matlab        Matlab     

EasyFPGA030 example code

This source code is the EasyFPGA030 example code. Welcome to download and try. Thank you all for your support!...
  verilog      Verilog     

Digital Alarm Clock FPGA

The aim this project is to implement the functionality of a digital alarm clock on a FPGA. As soon as the FPGA is switched on, the clock starts. The alarm can be set using the dip-switches provided on the FPGA board. This is indicated through the LEDs of the corresponding dip swi...
  verilog      Verilog     

FPGA VGA interface

VGA interface based on FPGA examples here, we must first consider vga_interface.v to support image resolutions, that is, 16x 16. So RAM Storage space required is 16Bits x 16Words. RAM, like FIFO, to access the RAM when they are needed Up to xx_En_Sig signals. Because the RAM contains 16Bits Write_...
  verilog      Verilog     

Study on Turbo Code decoder and FPGA implementation.

Altera Quartus II software platform completed the decoding of Turbo codes based on Log-MAP algorithm for FPGA design and implementation. In Turbo yards of FPGA design and achieved part, main for has Turbo yards of compiled yards device in the all important module for has design and achieved, such as...
  vhdl      VHDL     

Design of UART based on FPGA

This is the more successful graduate students during the design of curriculum design. Prepared by Verilog to send, receive, has top-level modules! FPGA Development Board can be run....
  verilog      Verilog     

FP Growth tree

FP Growth is the one of the algorithm in frequent item set mining. It is used to find the frequent item set in a database. It will give the output in tree structure format. It is more efficient than apriori algorithm because there is no candidate generation. Strong association rule is generated as t...
  Algorithm        Java     

基于Apriori、FP-Growth及Eclat算法的频繁模式挖掘源程序

关联分析频繁模式挖掘Apriori、FP-Growth及Eclat算法的JAVA及C++实现。三种算法实现的完整源码工程、源文件、PPT、测试数据及输出示例 ,包括Apriori、FP-Growth及Eclat三种算法的频繁模式挖掘源程序...
  Algorithm        Java     

FPU Floating point unit verilog VHDL

FPU (Floating Point Unit) is very useful in the moden ASIC and SOC designs. This module has been verified by FPGA and EDA env. But if you want to use it in a real project, please verify it with some formal method. ...
  verilog      Verilog     

Hirose_FPc_hf23

Hirose_FPc_hf23 Hirose_FPc_hf23 Hirose_FPc_hf23 Hirose_FPc_hf23...
  Other      VHDL     

FPGA Receiver in HDL projects Implementation of USB

FPGA Receiver in HDL projects Implementation of USB   main idea is to develop a receiver application which works for all applications. This receiver is implemented using VHDL USB2.0. We will test this receiver by downloading it in to FPGA. In this project Universal Seria...
  Windows        Matlab     

FPGA VGA control program

FPGA control VGA Verilog programs containing detailed notes, and has been verified on the CRT monitor through...
  Algorithm        C++     

FPGA source audio signal Analyzer

Audio signal through consists of the OPAMP and the resistance of the 50Ohm impedance matching circuit to meet the input impedance 50 Ohm system requirements, calculation of signal power. In order to ensure that this signal is undistorted sampled signals through the cut-off frequency for the 10Khz an...
  vhdl      VHDL     

"Original" display __ __verilog_ _FPGA control _1602 debugging notes

FPGA control principle and LCD1602 debugging notes source code This information came from Baidu bases (http://wenku.Baidu.com/) You now see the document is used to hold rice Baidu base generated by the Download Manager This document's original address from Thank you for your support Hold rice...
  verilog      Verilog     

DFPD algorithm: a low complexity Demosaicing algorithm with high PSNR

DFPD 是 Directional Filtering and a posteriori Decision Acronym for computational complexity is low, high frequency processing effects are better than some of the high complexity of algorithms....
  Algorithm        Matlab     

Ledbanner in verilog code using FPGA SPARTAN-3E

Ledbanner in verilog code using FPGA SPARTAN-3E is displaying 0-9 in 2 seven segment display.  It will go from left to rigth or vise versa. And will reset fuction when press reset botton....
  verilog      Verilog     

Using FPGA to realize the electronic clock

It is written in the Verilog language is a digital clock program, and run successfully on the FPGA Development Board. Compared to other languages veilog language is more concise, this program includes various modules, you can develop simulations on the Board....
  verilog      Verilog     

AD9516 PLL chip FPGA SPI configuration program

Prepared in the FPGA configuration through the SPI bus external PLL chip AD9516 program through Board-level debug, validation is available. Programs through a state machine, you will need to configure the register values for the data format sent to SPI bus....
  Driver Development      VHDL     

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