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FP Growth tree

14 hours ago    By:Raja sekaran      View:51      Download:0

FP Growth is the one of the algorithm in frequent item set mining. It is used to find the frequent item set in a database. It will give the output in tree structure format. It is more efficient than apriori algorithm because there is no candidate generation. Strong association rule is generated as t...

Algorithm Java

FP-Growth java code

2014-12-20 08:45    By:Pradeep      View:38      Download:0

FP-Growth java code When compiled the software can be invoked in the normal manner using the Java interpreter: java APPLICATION_CLASS_FILE_NAME If you are planning to process a very large data set it is a good idea to grab some extra memory. For example: java -Xms600m...

Java Development Java

weka Genetic Programming

2014-12-14 08:03    By:milad      View:35      Download:0

To the right of the status box is the weka status icon. When no processes are running, the bird sits down and takes a nap. The number beside the × symbol gives the number of concurrent processes running. When the system is idle it is zero, but it increases as the number of processes increases. W...

Java Development Java

Matlab to weka converter source code

5 hours ago    By:pinki      View:149      Download:0

This code will convert a weka supported file into .mat file and also a matlab file into weka supported file. Using this code, you need not to write separate matlab code for a dataset. Just provide the dataset and you can get its .mat file.  ...

Matlab Matlab

weka, Decision Tree for 1 year salaries analysis

2014-11-26 06:42    By:nimilios      View:12      Download:0

weka, Decision Tree for 1 year salaries analysis with Persian description in word format. Extensions are .arff format, and we use j48 data to do this work....

Computer Cluster Java

EasyFPGA030 example code

2014-12-09 06:03    By:yfw      View:48      Download:0

This source code is the EasyFPGA030 example code. Welcome to download and try. Thank you all for your support!...

verilog Verilog

FPGA digital photo frame

2014-12-18 01:45    By:liumin102003      View:29      Download:0

FPGA digital photo frame, read to achieve SD card pictures show that good code style, has the detailed  annotation, very useful for beginners, Hope will be helpful, thank you!...

Embeded VHDL

VFP DLL callback function is used to write Windows Service service programs

2014-12-20 20:12    By:xiaodao      View:104      Download:0

VFP no callback function using external DLL implements a callback. Under Windows service implemented as a register, log out, run, stop this function. VFP program can also be started as a service. Sell, improper please make perfect....

Windows VB

Digital Alarm Clock FPGA

2 hours ago    By:thuanbk2010      View:160      Download:0

The aim this project is to implement the functionality of a digital alarm clock on a FPGA. As soon as the FPGA is switched on, the clock starts. The alarm can be set using the dip-switches provided on the FPGA board. This is indicated through the LEDs of the corresponding dip swi...

verilog Verilog

Ov5620 used in FPGA

2014-12-17 21:38    By:ay0512040135      View:79      Download:1

Ov5620 used in FPGA, the program's function is to drive the camera OV5620 and data output through the VGA interface, external monitor See the webcam image....

verilog VHDL

FPGA VGA interface

12 hours ago    By:HELLOJJ      View:81      Download:0

VGA interface based on FPGA examples here, we must first consider vga_interface.v to support image resolutions, that is, 16x 16. So RAM Storage space required is 16Bits x 16Words. RAM, like FIFO, to access the RAM when they are needed Up to xx_En_Sig signals. Because the RAM contains 16Bits Write_...

verilog Verilog

Study on Turbo Code decoder and FPGA implementation.

2014-12-20 09:16    By:jerry_zjr      View:56      Download:0

Altera Quartus II software platform completed the decoding of Turbo codes based on Log-MAP algorithm for FPGA design and implementation. In Turbo yards of FPGA design and achieved part, main for has Turbo yards of compiled yards device in the all important module for has design and achieved, such as...

vhdl VHDL

FPGA VGA display experiments

11 hours ago    By:lulei      View:149      Download:1

This is an original VGA interface generation code. Is allowed to experiment in a certain size of image displayed on the computer monitor. Full realization of FPGA and PC monitors of the same letter. Code design is original....

verilog VHDL

FPGA digital clock display

2014-12-20 03:12    By:lcoliny      View:62      Download:0

FPGA clock display program, in accordance with the normal time, adjustable frequency, digital display, 00-00-00,-can be changed in the middle of it. Using a nested loop structure...

verilog VHDL

Based on Apriori, Eclat and FP-Growth algorithm for frequent pattern mining from source code

2014-12-19 03:43    By:guanhang      View:71      Download:0

Correlation analysis of Apriori and Eclat and FP-Growth algorithm for frequent pattern mining JAVA and C++ implementation. Three algorithms of integrity of the source code, source files, PPT, test data and output examples, including Apriori, three Eclat and FP-Growth algorithm for frequent pattern m...

Algorithm Java

FPU Floating point unit verilog VHDL

8 hours ago    By:stoverson      View:206      Download:3

FPU (Floating Point Unit) is very useful in the moden ASIC and SOC designs. This module has been verified by FPGA and EDA env. But if you want to use it in a real project, please verify it with some formal method. ...

verilog Verilog

high speed ADC-ADC08D1000 comunication in FPGA

2014-12-16 23:17    By:artin      View:41      Download:0

This is a program developed by Arron lee, in order to control ADC08D1000 Analog-to-digital device in FPGA, Xilinx Virtex-4 SX35 FPGA is applied here, the DCM is used to control the clock path in FPGA, the clock source is AD9517 which controled by serial port in FPGA...

vhdl VHDL


2013-12-22 22:59    By:tianson      View:19      Download:0

Hirose_FPc_hf23 Hirose_FPc_hf23 Hirose_FPc_hf23 Hirose_FPc_hf23...

Other VHDL

SFP to Eternet transfer data

2014-11-07 05:11    By:ka-31      View:31      Download:0

Code for ML-605 xilinx board, with extention board S14-S (4sFP ports). Project for transfer data from optical line to sFP-module to rj-45 ethernet and receiving on PC. Using Virtex-6 Tri-Mode Ethernet MAC Wrapper.PC1 (Ethernet)-> media converter (1,25Gb/s) -> optical line -> sFP-module(1,25...

TCP/IP Verilog
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